IDT77105L25TF8 IDT, Integrated Device Technology Inc, IDT77105L25TF8 Datasheet - Page 8

• Manufacturer Part Number: IDT77105L25TF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77105L25TF8

• Data Rate: 25.6Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

symbol-synchronized. Synchronization is established when it receives a
command byte, usually the start-of-cell command preceding the first
received cell.
the line is deemed 'bad'. The interrupt status register contains a Good
Signal Bit (address 0x01, bit 6 set to 0 = Bad signal initially) which shows
the status of the line per the following algorithm:
set to 7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024
cycles = 204.8 symbols) and no "bad symbol" has been received, the
counter decreases by one (i.e., from 7 to 6). However, if at least one
"bad symbol" is detected during these 1,024 clocks, the counter is
increased by one with a maximum of 7 (i.e., from 6 back to 7). The Good
Signal Bit is set to 1 when this counter reaches 0. The Good Signal Bit
could be set to 1 as quickly as 1,433 symbols (204.8 x 7) if no bad
symbols have been received.
a "Good" status). When the clock ticks for 1,024 cycles (32MHz clock,
1,024 cycles = 204.8 symbols) and there is at least one "bad symbol",
the clock increases one (i.e., from 0 to 1). If it detects all "good symbols"
and no "bad symbols" in the next time period, the counter decreases one
(i.e., from 1 back to 0). The "Bad Signal" is declared when the counter
reaches 7. The Good Signal Bit could be set to 0 as quickly as 1,433
symbols (204.8 x 7) if at least one "bad symbol" is detected in each
204.8 symbols of seven consecutive groups of 204.8 symbols.
IDT77105
Upon reset or line re-connect, the IDT77105 receiver is typically not
The IDT77105 monitors line conditions and can provide an interrupt if
To declare “Good Signal” (from "Bad" to "Good"):
There is an up-down counter that counts from 7 to 0 and is initially
To declare 'Bad Signal' (from "Good" to "Bad"):
The same up-down counter counts from 0 to 7 (being at 0 to provide
Rx +
Rx
Decoding
NRZI
OSC
Synthesizer
32.0MHz
& PLL
Clock
5
Decoding
5b/4b
8 of 24
Figure 2
Interface
Control -
RECV
Octet
interface is used as the data path interface between the IDT77105 PHY
and other system elements such as the Segmentation and Reassembly
(SAR) device, or switching systems.
Overview
Overview
Overview
Overview
nizing clocks which are controlled by the SAR or other system compo-
nents. Transfer of data is synchronized at the cell level through the use
of a Start of Cell signal. This signal is asserted when the data transfer
path contains the first byte of a cell.
zation, flow control signals are provided to allow both the external device
and the PHY to throttle the data transfer rate.
external device. The PHY also provides an RxEmpty signal to indicate
that no valid data is ready for transfer out of the PHY. This signal is
active if another read would cause a PHY buffer underflow. Along with
RxEmpty, RxClav (Receive Cell Available) indicates that a complete cell
has been received and is ready for transfer. Likewise, Transmit data is
also transferred using similar controls and handshake signals.
to allow control of several functions such as Header Error Control (HEC)
processing, diagnostics, and error notification/management.
2 Cells
UTOPIA Interface
UTOPIA Interface
UTOPIA Interface
UTOPIA Interface
The 'UTOPIA' (Universal Test & Operations PHY Interface for ATM)
Cell data is transferred via separate Transmit and Receive synchro-
Since the PHY layer uses external clocks for data transfer synchroni-
Receive data is transferred when the RxEnb signal is asserted by an
The Status and Control interface for the IDT77105 PHY is provided
4
R xRef
4
8
Command
Detection,
& Decode
RxSOC
Removal,
Byte
RxData
RxClk
R xEm pt y
R xEnb
Reset
4
4
Scramble
Scrambler
3445 drw 04
Nibble
PRNG
De-
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September 11, 2000