IDT77V1254L25PG IDT, Integrated Device Technology Inc, IDT77V1254L25PG Datasheet - Page 17

• Manufacturer Part Number: IDT77V1254L25PG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1254L25PG

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

document af-phy-0017. Utopia Level 1 is essentially the same as Utopia
Level 2, but without the addressing, polling and selection features.
RXCLAV and RXEN signals for each channel of the 77V1254L25. There
are just one each of the TXSOC and RXSOC signals, which are shared
across all four channels.
Level 1 also offers the option of a byte mode protocol. Bit 1 of the Master
Control Registers is used to program whether the UTOPIA Level 1 bus is
in cell mode or byte mode. In byte mode, the PHY is allowed to control
data transfer on a byte-by-byte basis via the TXCLAV and RXCLAV
signals. In cell mode, TXCLAV and RXCLAV are ignored once the
transfer of a cell has begun. In every other way the two modes are iden-
tical. Cell mode is the default configuration and is the one described
later.
inputs to the 77V1254L25. All Utopia signals are timed to these clocks.
IDT77V1254L25
The UTOPIA Level 1 MULTI-PHY interface is based on ATM Forum
Instead of addressing, this mode utilizes separate TXCLAV, TXEN,
In addition to Utopia Level 2's cell mode transfer protocol, Utopia
The Utopia 1 signals are summarized below:
Transmit and receive both utilize free running clocks, which are
Figure 6 Utopia Level 2 Data Format and Sequence
Last
First
TXDATA[7:0]
TXPARITY
TXSOC
TXEN
TXCLAV[3:0]
TXCLK
RXDATA[7:0]
RXPARITY
RXSOC
RXEN
RXCLAV[3:0]
RXCLK
Bit 15
[3:0]
[3:0]
Payload byte 45
Payload byte 47
Payload byte 1
Payload byte 3
Header byte 1
Header byte 3
Header byte 5
Payload byte 5
Payload byte 46
Payload byte 48
Payload byte 2
Payload byte 4
Payload byte 6
Header byte 2
Header byte 4
stuff byte
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
PHY to ATM
ATM to PHY
Bit 0
17 of 48
available) to indicate that it has room in its transmit FIFO to accept at
least one 53-byte ATM cell. When the ATM layer device is ready to begin
passing the cell, it asserts TXEN (transmit enable) and TXSOC (start of
cell), coincident with the first byte of the cell on TXDATA. TXEN remains
asserted for the duration of the cell transfer, but the ATM device may
deassert TXEN at any time once the cell transfer has begun, but data is
transferred only when TXEN is asserted.
prepared to receive data. As with transmit, it may be asserted or deas-
serted at any time. Note, however, that not more than one RXEN should
be asserted at a time. Also, once a given RX port is selected, that port's
FIFO must be emptied of cells (as indicated by RXCLAV) before a
different RX port may be enabled.
asserted for one clock, coincident with the first byte of each cell. Odd
parity is utilized across each 8-bit data field.
1, and Figures 15 to 21 are examples of the Utopia Level 1 handshake.
In the transmit direction, the PHY first asserts TXCLAV (transmit cell
In the receive direction, RXEN indicates when the ATM device is
In both transmit and receive, TXSOC and RXSOC (start of cell) is
Figure 8 shows the data sequence for an ATM cell over Utopia Level
December 2004