IDT77V107L25PFI8 IDT, Integrated Device Technology Inc, IDT77V107L25PFI8 Datasheet - Page 3

• Manufacturer Part Number: IDT77V107L25PFI8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V107L25PFI8

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 1
• Type Of Atm Phy Interface: UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Name
RXD+, RXD-
TXD+, TXD-
Signal Name
AD[7:0]
ALE
CS
RD
WR
Signal Name
RXADDR[4:0]
RXCLAV
RXCLK
RXDATA[7:0]
RXEN
RXPARITY
RXSOC
TXADDR[4:0]
TXCLAV
TXCLK
TXDATA[7:0]
TXEN
IDT77V107
Pin Number
85, 84
93, 92
Pin Number
67, 66, 65, 64,
62, 61, 60, 59
58
57
56
55
Pin Number
37, 36, 35, 34,
33
30
28
39, 40, 41, 42,
44, 45, 46, 47
29
38
31
19, 18, 17, 16,
15
24
27
14, 13, 12, 11,
10, 9, 8, 7
21
I/O
In
Out
I/O
In/Out Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this bus when
In
In
In
In
I/O
In
Out
In
Out
In
Out
Out
In
Out
In
In
In
Positive and negative transmit differential output pair.
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling edge of ALE.
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by deasserting
Utopia Receive Address. Address for polling and selecting a Utopia port/PHY.
Utopia Receive Cell Available. “1” indicates that the receive FIFO contains a complete received cell. “0” indicates that
Utopia Receive Data. When one of the four ports is selected, the 77V107 transfers received cells to an ATM device
Utopia Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA bus.
Utopia Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.
Utopia Transmit Address. Address for polling and selecting a Utopia port/PHY.
Utopia Transmit Cell Available. “1” indicates that the transmit FIFO has room available for at least one complete cell.
Utopia Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA bus.
Signal Description
Positive and negative receive differential input pair.
Signal Description
a read is performed. Input data is sampled at the completion of a write operation.
ALE must be low when the AD bus is being used for data.
Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain asserted
at all times if desired.
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by deasserting
WR and asserting RD and CS.
RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is deasserted.
Signal Description
it does not. RXCLAV is high impedance when RXADDR[4:0] does not match the internally programmed Utopia
address.
Utopia Receive Clock. This is a free running clock input.
across this bus. Also see RXPARITY.
Utopia Receive Data Parity. Odd parity over RXDATA[7:0].
“0” indicates that it does not. TXCLAV is high impedance when TXADDR[4:0] does not match the internally pro-
grammed Utopia address.
Utopia Transmit Clock. This is a free running clock input.
Utopia Transmit Data. An ATM device transfers cells across this bus to the 77V107 for transmission. Also see TXPAR-
ITY.
Table 1 Signal Descriptions (Part 1 of 2)
UTOPIA Bus Signals
Utility Bus Signals
Line Side Signals
3 of 24
December 2004