IDT77V107L25PFI8 IDT, Integrated Device Technology Inc, IDT77V107L25PFI8 Datasheet
IDT77V107L25PFI8
Specifications of IDT77V107L25PFI8
Related parts for IDT77V107L25PFI8
IDT77V107L25PFI8 Summary of contents
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Features List ! Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions of the Physical Layer ! Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5 specifications for 25.6 Mbps physical interface ! Also operates at 51.2Mbps ! ...
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IDT77V107 uniquely defined such that this bit sequence cannot be duplicated by concatenating any two other valid symbols. The escape symbol is used incombination with a second symbol to form command symbol pairs. Two command symbol pairs are defined as ...
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IDT77V107 Signal Name Pin Number I/O Signal Description RXD+, RXD- 85 Positive and negative receive differential input pair. TXD+, TXD- 93, 92 Out Positive and negative transmit differential output pair. Signal Name Pin Number I/O Signal Description AD[7:0] ...
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IDT77V107 TXPARITY 20 In Utopia Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in the Interrupt Status Registers, as enabled in the Master Control Register. No other action is taken in the event of ...
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IDT77V107 Functional Description Transmission convergence (TC) sub layer Introduction The TC sub layer defines the line coding, scrambling, data framing and synchronization. Under control of a switch interface or Segmenta- tion and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts ...
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IDT77V107 Transmission Description Refer to Figure 4 on the previous page. Cell transmission begins with the PHY-ATM Interface. An ATM layer device transfers a cell into the 77V107 across the Utopia transmit bus. This cell enters a 3-cell deep transmit ...
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IDT77V107 Bit 7 Bit 0 Header Byte 1 Header Byte 2 Header Byte 3 Header Byte 4 UDF Payload Byte 1 Payload Byte 48 3505 drw 52 UDF = User Defined Field (or HEC) Figure 3 ATM Cell Format Note ...
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IDT77V107 To declare 'Bad Signal' (from "Good" to "Bad"): The same up-down counter counts from (being provide a "Good" status). When the clock ticks for 1,024 cycles (32MHz clock, 1,024 cycles = 204.8 symbols) ...
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IDT77V107 polling polling: TxCLK TxADDR[4:0] 1F N+3 High-Z TxCLAV N+1 TxEN TxData[7:0], P44 P45 TxPARITY TxSOC PHY N cell transmission to: polling polling: TxCLK TxADDR[4:0] 1F N+3 High-Z TxCLAV N+1 TxEN TxData[7:0], P46 P47 TxPARITY TxSOC PHY N cell transmission ...
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IDT77V107 polling: TxCLK TxADDR[4:0] 1F N+3 High-Z TxCLAV N+1 TxEN TxData[7:0], P28 P29 TxPARITY TxSOC PHY M cell transmission to: polling polling: RxCLK RxADDR[4:0] N+3 1F RxCLAV N+3 RxEN RxData[7:0], P44 P45 RxPARITY RxSOC PHY N cell transmission to: polling ...
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IDT77V107 polling polling: RxCLK RxADDR[4:0] N+3 1F RxCLAV N+3 RxEN RxData[7:0], P47 P48 RxPARITY RxSOC PHY N+3 cell transmission to: polling polling: RxCLK RxADDR[4:0] N+3 1F RxCLAV N+3 RxEN RxData[7:0], P28 P29 RxPARITY RxSOC PHY M cell transmission from: Figure ...
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IDT77V107 Control and Status Interface Utility Bus The Utility Bus is a byte-wide interface that provides access to the registers within the IDT77V107. These registers are used to select desired operating characteristics and functions, and to communicate status to external ...
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IDT77V107 Diagnostic Functions 1. Loopback There are two loopback modes supported by the 77V107. The loop- back mode is controlled via bits 1 and 0 of the Diagnostic Control Regis- ters: Normal Mode Figure 12 shows normal operating conditions: data ...
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IDT77V107 2. Counters Several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions anticipated that these counters will be polled from time to time (user selectable) to evaluate performance. ! Symbol Error ...
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IDT77V107 Component Value 620 10k R7 10k R10 82 C1 470pF C2 470pF C3 0 3.3 H Table 2 Analog Component Values Master Control ...
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IDT77V107 Interrupt Status Register Address:0x01 Bit Type Initial State 7 0 Reserved Bad Signal Good Signal Bit See definitions earlier in this data sheet Good Signal 0 - Bad Signal 5 sticky 0 HEC ...
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IDT77V107 LED Driver and HEC Status/Control Registers Address:0x03 Bit Type Initial State R enable checking 5 R enable calculate & replace 4,3 R cycle empty ...
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IDT77V107 Interrupt Mask Register Address:0x07 Bit Type Initial State R interrupt enabled 4 R interrupt enabled 3 R interrupt enabled 2 R interrupt enabled 1 R/W 0 ...
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IDT77V107 Recommended Operating Temperature and Supply Voltage Ambiant Grade Temperature AGND Industrial - + Electrical Characteristics (All Pins except TXD+/- and RXD+/-) Symbol Parameter I Input Leakage Current (TxADDR, RxADDR, M0, DA) LI Input Leakage ...
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IDT77V107 Symbol t4 TxDATA[7:0], TxPARITY Hold Time to TxCLK t5 TxADDR[4:0], Setup Time to TxCLK t6 TxADDR[4:0}, Hold Time to TxCLK t7 TxSOC, TxEN Setup Time to TxCLK t8 TxSOC, TxEN Hold Time to TxCLK t9 TxCLK to TxCLAV High-Z ...
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IDT77V107 Utility Bus Read Cycle Name Min Max Unit Tas 10 ____ ns Address setup to ALE Tcsrd 0 ____ ns Chip select to read enable Tah 5 ____ ns Address hold to ALE Tapw 10 ____ ns ALE min ...
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IDT77V107 OSC, TXREF and Reset Timing Symbol Tcyc OSC cycle period (25.6 Mbps) (51.2 Mbps) Tckh OSC high time Tckl OSC low time Tcc OSC cycle to cycle period variation Ttrh TXREF High Time Ttrl TXREF Low Time Trspw Minimum ...
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IDT77V107 Package Drawing 100 1 SYMBOL MIN 0. 0.17 Dimensions are in millimeters For the complete package drawing, see PSC4036.pdf in the ...
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IDT77V107 Ordering Information IDT NNNNN A Device Type Power Revision History 1/20/2000: ADVANCE INFORMATION. Initial release. 2/18/2000 PRELIMINARY. Initial release. 1/4/2001 FINAL. DPI interface option removed, package drawing added, power consumption and Utopia timing limits improved. Corrections to Diag- nostic ...