85314BGI-01T IDT, Integrated Device Technology Inc, 85314BGI-01T Datasheet - Page 13

• Manufacturer Part Number: 85314BGI-01T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of 85314BGI-01T

• Number Of Clock Inputs: 2
• Output Frequency: 700MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.8V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

This section provides information on power dissipation and junction temperature for the ICS85314I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
T
85314BGI-01
ABLE
ABLE
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
6A. T
6B. T
Power (core)
Power (outputs)
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power
The equation for Tj is as follows: Tj =
Tj = Junction Temperature
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
85°C + 0.455W * 66.6°C/W = 115°C. This is well below the limit of 125°C.
JA
A
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
HERMAL
HERMAL
MAX
R
R
_MAX
ESISTANCE
ESISTANCE
MAX
= V
(3.465V, with all outputs switching) = 304mW + 151mW = 455mW
= 30.2mW/Loaded Output pair
CC_MAX
* I
JA
EE_MAX
JA
FOR
FOR
JA
JA
P
CC
= 3.8V * 80mA = 304mW
by Velocity (Linear Feet per Minute)
by Velocity (Linear Feet per Minute)
20-
= 3.8V, which gives worst case results.
20-
OWER
JA
PIN
PIN
D
* Pd_total + T
IFFERENTIAL
TSSOP, F
SOIC, F
C
www.idt.com
ONSIDERATIONS
ORCED
A
ORCED
13
114.5°C/W
73.2°C/W
83.2°C/W
46.2°C/W
-
TO
C
0
0
C
ONVECTION
-2.5V/3.3V LVPECL F
ONVECTION
65.7°C/W
39.7°C/W
98.0°C/W
66.6°C/W
200
200
JA
ICS85314I-01
must be used. Assuming a
L
OW
88.0°C/W
63.5°C/W
57.5°C/W
36.8°C/W
500
500
ANOUT
S
KEW
REV. F JULY 25, 2010
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UFFER
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