83940DYI-01LF IDT, Integrated Device Technology Inc, 83940DYI-01LF Datasheet - Page 13

• Manufacturer Part Number: 83940DYI-01LF
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of 83940DYI-01LF

• Number Of Clock Inputs: 2
• Output Frequency: 175MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Compliant

ICS83940I-01 Data Sheet
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, SSTL and other differential
signals. Both differential signals must meet the V
requirements. Figures 2A to 2C show interface examples for the
PCLK/nPCLK input driven by the most common driver types. The
Figure 2A. PCLK/nPCLK Input Driven by a
Figure 2C. PCLK/nPCLK Input Driven by an
Recommendations for Unused Input and Output Pins
Inputs:
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
LVCMOS_CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the LVCMOS_CLK input to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010
2.5V
3.3V
LVPECL
SSTL
3.3V LVPECL Driver
SSTL Driver
Zo = 60Ω
Zo = 60Ω
Zo = 50Ω
Zo = 50Ω
R3
120
R3
125Ω
2.5V
3.3V
R1
120
R1
84Ω
R4
125Ω
R4
120
R2
120
R2
84Ω
PCLK
nPCLK
PP
PCLK
nPCLK
3.3V
and V
3.3V
LVPECL
Input
LVPECL
Input
CMR
input
13
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
Figure 2B. PCLK/nPCLK Input Driven by a
Outputs:
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
3.3V
3.3V LVPECL
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
R5
100 - 200
3.3V LVPECL Driver with AC Couple
R6
100 - 200
Zo = 50Ω
Zo = 50Ω
©2010 Integrated Device Technology, Inc.
C1
C2
R3
84
3.3V
R1
125
R4
84
R2
125
PCLK
nPCLK
3.3V
LVPECL
Input