ICS83940DYI-01LF IDT, Integrated Device Technology Inc, ICS83940DYI-01LF Datasheet
ICS83940DYI-01LF
Specifications of ICS83940DYI-01LF
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ICS83940DYI-01LF Summary of contents
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... Pulldown CLK_SEL Pulldown PCLK 0 Pullup/Pulldown nPCLK Pulldown LVCMOS_CLK 1 ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 Features • Eighteen LVCMOS/LVTTL outputs, 23Ω typical output impedance • Selectable LVCMOS_CLK or LVPECL clock inputs • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, SSTL • ...
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... Input Pullup Resistor PULLUP Power Dissipation Capacitance C PD (per output) R Output Impedance OUT ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 Type Description Power Power supply ground. Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects LVCMOS_CLK input. When LOW, ...
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... Biased; NOTE 1 0 – Biased; NOTE NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels. ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 Clock LVCMOS_CLK De-selected Selected Outputs PCLK nPCLK Q[0:17 LOW 1 0 HIGH 0 Biased; NOTE 1 ...
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... Symbol Parameter V Power Supply Voltage DD V Output Supply Voltage DDO I Power Supply Current DD I Output Supply Current DDO ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Rating 3.6V -0. 0.3V DD -0. 0.3V DDO ±20mA 53.5°C/W (0 mps) -40°C to 125° 3.3V± ...
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... PCLK I Input Low Current IL nPCLK I Input Current IN V Peak-to-Peak Input Voltage PP V Common Mode Input Voltage; NOTE 1 CMR NOTE 1: Common mode voltage is defined as V ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 = 3.3V±5% or 2.5V±5 Test Conditions V = 3. 3. 3. 3.465V or 2.625V ...
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... NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 = V = 3.3V ± 5 -40° ...
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... NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 = 3.3V ± 5 2.5V ± 5%, T ...
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... NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 = V = 2.5V ± 5 -40° ...
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... The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental ...
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... Core/2.5V LVCMOS Output Load AC Test Circuit Part 1 V DDO Qx 2 Part 2 V DDO Qy 2 tsk(pp) Part-to-Part Skew ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 1.25V±5% SCOPE V DD, V DDO Qx LVCMOS GND -1.25V±5% 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit ...
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... ICS83940I-01 Data Sheet Parameter Measurement Information, continued 80% 20% Q[0:17 Output Rise/Fall Time nPCLK PCLK LVCMOS_CLK V DDO Q[0:17 Propagation Delay ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Q[0:17] 80% 20 Output Duty Cycle/Pulse Width/Period 11 V DDO PERIOD 100% odc = t PERIOD ...
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... This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 line impedance. For most 50Ω applications, R3 and R4 can be 100Ω ...
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... LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 input interfaces suggested here are examples only. If the driver is and V input from another vendor, use their termination recommendation. Please ...
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... This calculation is only an example. Tj will vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). θ Table 6. Thermal Resistance JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 * ( 3.465V *(26mA + 28mA) = 187.11mW DD DDO number of outputs = 9pF * 175MHz * (3 ...
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... Table 7. vs. Air Flow Table for a 32 Lead LQFP JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS83940I-01 is: 819 ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER θ vs. Air Flow 53.5°C/W 48.0° ...
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... Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 θ 0° ccc Reference Document: JEDEC Publication 95, MS-026 ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7° 0.10 16 ©2010 Integrated Device Technology, Inc. ...
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... Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Package ...
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ICS83940I-01 Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to ...