83940DY IDT, Integrated Device Technology Inc, 83940DY Datasheet - Page 7

• Manufacturer Part Number: 83940DY
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of 83940DY

• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

IDT™ / ICS™ LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
ICS83940D
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
83940DY
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
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1k
Integrated
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Systems, Inc.
10k
www.icst.com/products/hiperclocks.html
O
A
FFSET
DDITIVE
100k
LVPECL-
F
ROM
P
C
HASE
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7
ARRIER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
TO
J
F
ITTER
REQUENCY
-LVCMOS / LVTTL F
1M
Input/Output Additive Phase Jitter
(H
Z
)
at 155.52MHz = 0.03ps (typical)
L
OW
10M
S
ANOUT
KEW
REV. B JUNE 15, 2004
, 1-
B
TO
UFFER
-18
100M
ICS83940D
TSD