ICS8524AY IDT, Integrated Device Technology Inc, ICS8524AY Datasheet - Page 12

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ICS8524AY

Manufacturer Part Number
ICS8524AY
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS8524AY

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
500MHz
Output Logic Level
HSTL
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TQFP EP
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS8524AYLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ICS8524AYLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
This section provides information on power dissipation and junction temperature for the ICS8524.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8524 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
air flow of 500 linear feet per minute and a multi-layer board, the appropriate value is 15.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
8524AY
ABLE
6. T
Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Power (core)
Power (outputs)
If all outputs are loaded, the total power is 22 * 32.8mW = 721.6mW
Total Power
The equation for Tj is as follows: Tj = θ
Tj = Junction Temperature
θ
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
85°C + 1.484W * 15.1°C/W = 107.4°C. This is well below the limit of 125°C.
JA
A
HERMAL
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
R
ESISTANCE
MAX
_MAX
MAX
= V
(3.465V, with all outputs switching) = 762.3mW + 721.6mW = 1483.9mW
DD_MAX
= 32.8mW/Loaded Output pair
θ θ θ θ θ
JA
* I
FOR
DD_MAX
θ θ θ θ θ
64-
JA
P
DD
by Velocity (Linear Feet per Minute)
= 3.465V * 220mA = 762.3mW
PIN
= 3.3V + 5% = 3.465V, which gives worst case results.
OWER
TQFP, E-P
JA
* Pd_total + T
C
www.idt.com
AD
ONSIDERATIONS
F
A
12
ORCED
22.3°C/W
C
D
0
ONVECTION
IFFERENTIAL
17.2°C/W
200
-
TO
-HSTL F
JA
must be used. Assuming an
L
OW
15.1°C/W
S
500
ANOUT
KEW
REV. B DECEMBER 6, 2010
ICS8524
, 1-
B
TO
UFFER
-22

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