ICS8524AY IDT, Integrated Device Technology Inc, ICS8524AY Datasheet
ICS8524AY
Specifications of ICS8524AY
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ICS8524AY Summary of contents
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G D ENERAL ESCRIPTION The ICS8524 is a low skew, 1-to-22 Differential-to-HSTL Fanout Buffer . The ICS8524 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, ...
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ABLE IN ESCRIPTIONS ...
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ABLE IN HARACTERISTICS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S ...
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T 4D. LVPECL DC C ABLE HARACTERISTICS ...
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The spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most ...
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P ARAMETER 1.8V±0.2V 3.3V± DDO HSTL GND 0V 3.3V C /1. ORE UTPUT OAD PART 1 nQx Qx PART 2 nQy Qy tsk(pp ART TO ART KEW 80% Clock ...
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IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both V must meet the V and V input requirements. Figures 3A PP CMR to 3E show interface examples ...
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LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING and V input requirements. Figures show CMR interface examples for the PCLK/nPCLK input driven ...
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S E CHEMATIC XAMPLE Figure 5 shows a schematic example of the ICS8524. In this example, the input is driven by a HSTL driver. The decoupling 1. Ohm Ohm LVHSTL Driv er R9 R10 ...
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This section provides information on power dissipation and junction temperature for the ICS8524. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8524 is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 7. F IGURE T o calculate worst case power dissipation into the ...
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ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs ...
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ACKAGE UTLINE UFFIX FOR ABLE ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...