ICS853111BY IDT, Integrated Device Technology Inc, ICS853111BY Datasheet - Page 10

• Manufacturer Part Number: ICS853111BY
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS853111BY

• Lead Free Status / RoHS Status: Not Compliant

R
I
PCLK/nPCLK I
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
IDT
NPUTS
ERMINATION FOR
ECOMMENDATIONS FOR
ICS853111B
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
™
RTT =
/ ICS
™
((V
1-TO-10, LVPECL/ECL FANOUT BUFFER
F
FOUT
OH
IGURE
+ V
NPUTS
OL
3A. LVPECL O
) / (V
3.3V LVPECL O
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
U
NUSED
Z
o
50Ω
UTPUT
I
NPUT AND
UTPUTS
T
RTT
ERMINATION
50Ω
V
CC
O
FIN
- 2V
UTPUT
P
INS
10
ance techniques should be used to maximize operating fre-
quency and minimize signal distortion. Figures 3A and 3B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
O
LVPECL O
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
UTPUTS
FOUT
UTPUTS
F
IGURE
3B. LVPECL O
Z
Z
o
o
= 50Ω
= 50Ω
ICS853111BY REV. C JANUARY 13, 2009
125Ω
84Ω
UTPUT
3.3V
125Ω
84Ω
T
ERMINATION
FIN