MPC941FAR2 IDT, Integrated Device Technology Inc, MPC941FAR2 Datasheet - Page 6

• Manufacturer Part Number: MPC941FAR2
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of MPC941FAR2

• Number Of Clock Inputs: 2
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVPECL
• Mounting: Surface Mount
• Pin Count: 48
• Quiescent Current: 5mA
• Lead Free Status / RoHS Status: Not Compliant

IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to
AN1091 in the Timing Solutions data book (DL207/D).
distribution of signals is the method of choice. In a point-to-
point scheme, either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50 Ω
resistance to V
of DC current, and thus, only a single terminated line can be
driven by each output of the MPC941 clock driver. For the
series terminated case, however, there is no DC current
draw; thus, the outputs can drive multiple series terminated
lines.
terminated line vs two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC941 clock
driver is effectively doubled due to its capability to drive
multiple lines.
results of an output driving a single line vs two lines. In both
cases, the drive capability of the MPC941 output buffer is
more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC941. The output waveform
in
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 Ω series resistor plus the
IN
IN
Figure 2
The MPC941 clock driver was designed to drive high-
In most high performance clock networks, point-to-point
The waveform plots of
Figure 1. Single versus Dual Transmission Lines
Figure 1
MPC941
MPC941
Output
Output
14Ω
14Ω
Buffer
Buffer
shows a step in the
illustrates an output driving a single series
CC
/2. This technique draws a fairly high level
R
R
R
S
S
S
Figure 2
= 36Ω
= 36Ω
= 36Ω
Freescale
waveform. This
show the simulation
Z
Z
Z
O
O
O
= 50Ω
= 50Ω
= 50Ω
application note
APPLICATIONS INFORMATION
step is caused
OutA
OutB0
OutB1
6
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
unity reflection coefficient, to 2.5 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case, 4.0 ns).
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
At the load end, the voltage will double, due to the near
Since this step is well above the threshold region, it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 3. Optimized Dual Line Termination
Figure 2. Single versus Dual Waveforms
V
Z
R
R
V
Figure 3
O
L
L
MPC941
S
O
Output
14Ω
t
Buffer
2
D
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31 V
IN
= 3.8956
OutA
14Ω + 22Ω || 22Ω = 50Ω ||50Ω
S
( Z
should be used. In this case, the series
4
O
/ (R
25Ω = 25Ω
R
R
t
6
S
D
S
S =
= 3.9386
= 22Ω
+ R
OutB
TIME (ns)
22Ω
O
MPC941 REV. 8 APRIL 29, 2008
8
+ Z
Z
Z
O
O
O
))
= 50Ω
= 50Ω
10
12
14