TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 6

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

4.3
4.4
4.5
6
Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL)
Asynchronous Reset (ASYNCRESET)
Synchronous Reset (SYNCRESET)
TS81102G0
The input clock phase can be adjusted with an adjustable delay (from 250 to 750 ps). This is to
ensure a proper phase between the clock and input data of the DMUX.
Figure 4-3.
The asynchronous reset is a master reset of the port selection, which works on TTL levels. It is
active on the high level. During an asynchronous reset, the clock must be in a known state. It is
used to start the DMUX.
When it is active, it paralyzes the outputs (the output clock and output data remain at the same
level as before the asynchronous reset). When it comes back to its low level, the DMUX starts:
the outputs are active and the first processed data is on port A.
Figure 4-4.
The DMUX can be synchronously reset to a programmable state depending on the conversion
ratio. The clock must not be stopped during reset. The synchronization signal is a clock
(SyncRest) whose frequency is FS/8*n where n is an integer (n = 1,2,3 etc.) in 1:8 mode and
FS/4*n in 1:4 mode.
Asynchronous Reset
Synchronous Reset
SyncReset = FS/8
Port G selected
Port A selected
Port B selected
Port C selected
Port D selected
Port E selected
Port H selected
Port F selected
Port C selected
Port D selected
Port G selected
Port H selected
Port A selected
Port B selected
Port E selected
Port F selected
AsyncReset
Internal reset
CLKIN
pulse
DR/2
FS
2105D–BDC–07/05