TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 14

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

Table 5-3.
Note:
5.4
Table 5-4.
14
Parameter
Digital Inputs
DATA Input Voltages (ECL)
CTRL Input Voltages (TTL)
Parameter
Input Clock
Maximum clock frequency
Clock pulse width (high)
Clock pulse width (low)
Clock Path pipeline delay
Clock rise/fall time
Asynchronous Reset
Asynchronous Reset pulse width
Setup time from Asynchronous to Clkln
• Logic “0” voltage
• Logic “1” voltage
• Logic “0” voltage
• Logic “1” voltage
1:8 ratio
1:4 ratio
DR input clock
DR/2 input clock
1. The supply current I
Switching Performance and Characteristics
TS81102G0
- the minimum values correspond to all the output buffers at low level,
- the maximum values correspond to all the output buffers at high level,
- the typical values correspond to an equal sharing-out of the output buffers between high and low levels.
Electrical Specifications (Continued)
Switching Performances
50% clock duty cycle (CLKIN, CLKINB). Tj (typical) = 70°C.
Full temperature range: -40°C < Tc; Tj < 110°C.
(Guaranteed temperature ranges depend on the part number)
See Timing Diagrams
PLUSD
and the power dissipation depend on the state of the output buffers:
Figure 5-1 on page 17
TRCKIN
Symbol
TFCKIN
PWAR
FMAX
TCPD
TCPD
TSAR
TC1
TC2
Symbol
V
V
V
V
IL
IH
IL
IH
Level
Test
4
4
4
4
4
4
4
Level
Test
to
1
4
Figure 5-10 on page
1500
2000
Min
750
225
225
–
–
–
–
Min
-1.1
2.0
Value
1090
Typ
980
100
200
–
–
–
–
–
Value
Typ
23.
Max
–
–
–
–
–
–
–
Max
-1.6
0.6
MHz
Unit
ps
ps
ps
ps
ps
ps
ps
2105D–BDC–07/05
Unit
Note
V
V
V
V
(1)
(2)