TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 2

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TSEV81102G0TPZR3

Manufacturer Part Number
TSEV81102G0TPZR3
Description
Manufacturer
E2V
Datasheet

Specifications of TSEV81102G0TPZR3

Lead Free Status / RoHS Status
Not Compliant
1. Block Diagram
Figure 1. Block Diagram
2
8/10
master
TS81102G0
slave
even
latch
even
latch
Even Ports
8/10
BIST
8/10
Data Path
FS/8
mux
master
slave
latch
odd
latch
odd
Odd Ports
NAP
Port Selection Clock
8
ClkPar
Output
Clock
Data
8
B 2
control
Phase
shift register)
DataReady
generation
delay
mux
1
(8 stage
DR/DR
Counter
Clock Path
FS/8
RstGen
8
Counter
Status
Reset
2105D–BDC–07/05
delay