TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 24

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

6. Package Description
6.1
Table 6-1.
24
Type
Digital Inputs
Outputs
Control Signals
Synchronization
Power Supplies
Pin Description
TS81102G0
Enter Title of Manual Pin Description
Name
I[0…9]
Clkln
A[0…9] → H[0…9]
DR
RefA → RefH
ClklnType
RatioSel
Bist
SwiAdj
Diode
NbBit
AsyncReset
SyncReset
DMUXDelAdjCtrl
ADCDelAdjCtrl
ADCDelAdjln
ADCDelAdjOut
GND
V
V
V
EE
PLUSD
CC
Levels
Differential ECL
Differential ECL
Adjustable Logic
Single
Adjustable Logic
Differential
Adjustable Single
TTL
TTL
TTL
0V ± 0.5V
Analog
TTL
TTL
Differential ECL
Differential analog
input of ±0.5V
around 0V
common mode
Differential analog
input of ±0.5V
around 0V
common mode
Differential ECL
50Ω differential
output
Ground 0V
Power -5V
Adjustable power
from 0V to +3.3V
Power +5V
Comments
Data input.
On-chip 100Ω differential termination resistor.
Clock input (Data Ready ADC).
On-chip 100Ω differential termination resistor.
Data ready for port A to H.
Common mode is adjusted with V
SwiAdj. 50Ω termination possible.
Data ready for channel A to H.
Common mode is adjusted with V
SwiAdj. 50Ω termination possible.
Reference voltage for output channels A to H.
Common mode is adjustable with V
possible.
Data Ready or Datar Ready/2: logic 1: Data Ready.
DMUX ratio; logic 1: 1:4
Reset and Switch of built-in Self Test (BIST): logic 0: BIST active.
Swing fine adjustment of output buffers.
Diode for chip temperature measurement.
Number of bit 8 or 10: logic 1: 10-bit.
Asynchronous reset: logic 1: reset on.
Synchronous reset: active on rising edge.
Control of the delay line of Data Ready input:
differential input = -0.5V: delay = 250 ps
differential input = 0V: delay = 500 ps
differential input = 0.5V: delay = 750 ps
Control of the delay line for ADC:
differential input = - 0.5V: delay = 250 ps
differential input = 0V: delay = 500 ps
differential input = 0.5V: delay = 750 ps
Stand-alone delay adjust input for ADC.
Differential termination of 100Ω inside the buffer.
Stand-alone delay adjust output for ADC.
Common ground.
Digital negative power supply.
Common mode adjustment of output buffers.
Digital positive power supply.
PLUSD
PLUSD
PLUSD
. Swing is adjusted with
. Swing is adjusted with
. 50Ω termination
2105D–BDC–07/05