RAM5006E-016 Emerson Network Power, RAM5006E-016 Datasheet - Page 55

• Manufacturer Part Number: RAM5006E-016
• Manufacturer: Emerson Network Power

Specifications of RAM5006E-016

• Lead Free Status / RoHS Status: Compliant

4
Functional Description
Introduction
Features Summary
Table 4-1. MVME5100 General Features
This chapter provides a functional description for the MVME5100 Single Board Computer. The
MVME5100 is a high-performance product featuring PowerPlus II architecture with a choice of
PowerPC processors—either the MPC7410 with AltiVec™ technology for algorithmic intensive
computations or the low-power MPC750.
The MVME5100 incorporates a highly optimized PCI interface and memory controller enabling
up to 582MB memory read bandwidth and 640MB burst write bandwidth.
The optimization of the memory bus is as important as optimization of the system bus in order
to achieve maximum system performance. The MVME5100’s advanced PowerPlus II
Architecture supports full PCI throughput of 264MB without starving the CPU of its memory.
Additional features of the MVME5100 include dual Ethernet ports, dual serial ports and up to
17MB of Flash.
The table below lists the general features for the MVME5100. Refer to
Specifications, for additional product specifications and information.
Microprocessors and
Bus Clock Frequency
L2 Cache (Optional)
Memory
Main Memory
(SDRAM)
NVRAM
Memory Controller
PCI Host Bridge
Interrupt Controller
Feature
MVME51005E Single Board Computer Installation and Use (6806800A38B)
MPC7410 @400 or 500 MHz Internal Clock Frequency
MPC750 @450 MHz Internal Clock Frequency
Bus Clock Frequency up to 100 MHz
1MB (MPC750) or 2MB (MPC7410) using burst-mode
SRAM modules.
1MB via two 32-pin PLCC/CLCC sockets;
16MB Surface Mount
PC100 ECC SDRAM with 100 MHz bus
32MB to 512MB on board, expandable to
1.5GB via RAM500 memory mezzanine
32KB (4KB available for users)
Hawk System Memory Controller (SMC)
EEPROM, on-board programmable
Hawk PCI Host Bridge (PHB)
Hawk Multi-Processor Interrupt Controller (MPIC)
Specification
Appendix A,
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