MPC8536DS Freescale, MPC8536DS Datasheet - Page 90

• Manufacturer Part Number: MPC8536DS
• Manufacturer: Freescale

Specifications of MPC8536DS

• Lead Free Status / RoHS Status: Compliant

PCI
2.19.2
This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input
clock.
Figure 54
90
SYSCLK to output valid
Output hold from SYSCLK
SYSCLK to output high impedance
Input setup to SYSCLK
Input hold from SYSCLK
REQ64 to HRESET
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Rise time (20%–80%)
Failing time (20%–80%)
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3. All PCI signals are measured from OV
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
5. Input timings are measured at the pin.
6. The timing parameter t
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter t
9. The reset assertion timing requirement for HRESET is 100 μs.
Table 68
block)(signal)(state) (reference)(state)
example, t
relative to the SYSCLK clock, t
PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid
(V) state.
question for 3.3-V PCI signaling levels.
delivered through the component pin is less than or equal to the leakage current specification.
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
see
Bus Specifications .
provides the AC test load for PCI.
Section 22,
PCI AC Electrical Specifications
provides the PCI AC timing specifications at 66 MHz.
PCIVKH
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
“Clocking.”
Parameter
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V)
9
setup time
Output
SYS
PCRHFV
Table 68. PCI AC Timing Specifications at 66 MHz
indicates the minimum and maximum CLK cycle times for the various specified
SYS
for inputs and t
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
, reference (K) going to the high (H) state or setup time. Also, t
DD
Figure 54. PCI AC Test Load
/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV
Z
0
= 50 Ω
(first two letters of functional block)(reference)(state)(signal)(state)
Symbol
t
t
t
t
t
t
t
t
PCRHRX
t
t
PCKHOV
PCKHOX
PCKHOZ
PCRVRH
PCRHFV
PCIVKH
PCIXKH
PCICLK
PCICLK
1
10 × t
R
Min
2.0
3.0
0.6
0.6
—
—
10
0
0
L
SYS
= 50 Ω
(first two letters of functional
Max
OV
6.0
2.1
2.1
14
50
—
—
—
—
—
DD
/2
DD
Freescale Semiconductor
of the signal in
PCRHFV
clocks
clocks
Unit
ns
ns
ns
ns
ns
ns
ns
ns
for outputs. For
symbolizes
Notes
2, 3
2, 4
2, 5
2, 5
6, 7
—
—
2
7
8