MPC8536DS Freescale, MPC8536DS Datasheet

Page 1

... Two IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab, and IEEE Std 1588™-compatible controllers This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009. All rights reserved. ...

Page 2

... Part Numbers Fully Addressed by This Document . . 123 4.2 Part Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.3 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.1 Package Parameters for the MPC8536E FC-PBGA . 124 5.2 Mechanical Dimensions of the MPC8536E FC-PBGA125 6 Product Documentation 126 7 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . 126 Block Power Supply Decoupling Freescale Semiconductor ...

Page 3

... PowerQUICC III software The UART_SOUT[0:1] and TEST_SEL pins must be set to a proper state during POR configuration. Please refer to MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor e500 Core 512-Kbyte 32-Kbyte ...

Page 4

... NC SGND SRDS [5] [7] EN SD1_ SD1_ AVDD_ SD1_RX SD1_RX SV DD PLL_ SGND SGND IMP_CAL TDO SRDS [5] [7] TPD _TX Freescale Semiconductor AG AH USB1_ USB1_ 1 STP DIR USB1_ PWR- FAULT USB3_D USB3_D 3 [1] [0] USB3_D USB3_D 4 [3] [2] USB3_D USB3_ 5 [4] CLK USB3_D USB3_D 6 [6] ...

Page 5

... MA MA MECC 12 GND [11] [9] [7] MBA MECC MDQS MAPAR_ 13 [2] [6] [8] ERR MDQ MECC GND [27] [1] MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor MDQ MDQ MDQ MDQ GND [46] [47] [34] [56] MDQ MDQ MDQ MDQ GV DD [42] [43] [35] [60] MDQ ...

Page 6

... OV DD CD/GPIO CTS DAT GPIO[15] [0] [3] [4] UART_ UART_ SDHC_ SDHC_ GND SIN RTS DAT DAT [1] [1] [0] [1] IRQ[10]/ IRQ[9]/ PCI1_ SDHC_ SDHC_ DMA_ DMA_ DAT REQ CLK DREQ[2] DACK[2] [2] [2] IRQ[11]/ PCI1_ IIC2_ DMA_ OV DD SYSCLK GNT SDA DDONE[2] [2] Freescale Semiconductor ...

Page 7

... LDP LSYNC_ 27 GND GND [2] IN AVDD_ LSYNC_ 28 MVREF GND LBIU OUT MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor DETAIL C MDIC GV DD GND GND GND [0] LCS5/ LCS6/ MDQ LCS DMA_ DMA_ GND [18] [4] DREQ2 DACK2 MDQS MDQ ...

Page 8

... PCI1_ PCI1_ PCI1_ GND AD AD GND AD [14] [15] [11] PCI1_ PCI1_ PCI1_ PCI1_ [7] [9] [10] [12] PCI1_ PCI1_ PCI1_ PCI1_ C_BE [1] [4] [8] [0] PCI1_ PCI1_ PCI1_ PCI1_ GND CLK [0] [2] [3] PCI1_ POWER_ TMS EN [6] SD1_ SGND IMP_CAL TDO TCK TDI _TX Freescale Semiconductor ...

Page 9

... Request PCI1_REQ[0] Request PCI1_GNT[4:3]/GPIO[3:2] Grant PCI1_GNT[2:1] Grant PCI1_GNT[0] Grant PCI1_CLK PCI Clock MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 1. MPC8536E Pinout Listing Signal Name Package Pin Number PCI AB15,Y17,AA17,AC15, AB17,AC16,AA18, AD17,AE17,AB18, AB19,AE18,AC19, AF18,AE19,AC20, AF23,AE23,AC23, AH24,AH23,AG24, ...

Page 10

... A11,F9,E9,B12,A5, A12,D11,F7,E10,F10 A4,B5,B13 D3,H6,C4,G6 H10,K10,G10,H9 A9,J11,J6,A8,J13,H8 B9,H11,K6,B8,H13,J8 E5,H7,E6,F6 H15,K15 Local Bus Controller Interface Power Pin Type Notes Supply I/O GV — DD I/O GV — — — — DD I/O GV — DD I/O GV — — — — — — — — — — Freescale Semiconductor ...

Page 11

... UPM general purpose line 5 / Amux LCLK[0:2] Local bus clock LSYNC_IN Synchronization LSYNC_OUT Local bus DLL DMA_DACK[0:1] DMA Acknowledge /GPIO[10:11] MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Signal Name Package Pin Number K22,L21,L22,K23,K24, L24,L25,K25,L28,L27, K28,K27,J28,H28,H27, G27,G26,F28,F26,F25, E28,E27,E26,F24,E24, C26,G24,E23,G23,F22, G22,G21 K26,G28,B27,E25 L19 ...

Page 12

... AG9 AC9 AD5 USB Port 3 AH7,AG6,AH6,AG5, AG4,AH4,AG3,AH3 AG7 Power Pin Type Notes Supply I OV — — DD I I/O OV — — — 5 — — — — DD I/O OV — — — 5 — — — — DD I/O OV — — DD Freescale Semiconductor ...

Page 13

... Receive data TSEC1_RX_DV Receive data valid TSEC1_RX_ER Receive data error TSEC1_RX_CLK Receive clock Three-Speed Ethernet Controller (Gigabit Ethernet 3) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Signal Name Package Pin Number AG8 AH8 AH9 AH5 Programmable Interrupt Controller Y14 ...

Page 14

... V11 T11 eSDHC AH10 AH11 AG12,AH12,AH13, AG11 AE8,AC10,AF9,AA10 AG13 AG10 eSPI AF8 AD9 AD8 AE8,AC10,AF9,AA10 Power Pin Type Notes Supply O LV 5,9, 5 — — — — — — — 5,9, 5,9, 5,9, 5,9, — Freescale Semiconductor ...

Page 15

... SD2_RX[1:0] Receive data(-) SD2_PLL_TPD PLL test point Digital SD2_REF_CLK PLL Reference clock SD2_REF_CLK PLL Reference clock complement Reserved MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Signal Name Package Pin Number DUART AE11,Y12 AB12,AD12 AC12,AF12 AF10,AA12 interface AG21 ...

Page 16

... AF15 AH14 AC13 Power Pin Type Notes Supply — X2V 18 DD I/O OV — DD I/O OV — DD I/O OV — I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — — — — 2 — 6 6,9, 6, — — Freescale Semiconductor ...

Page 17

... PVDD LVDD GMAC 1 I/O supply TVDD GMAC 3 I/O supply GVDD SSTL2 DDR supply BVDD Local bus I/O supply MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Signal Name Package Pin Number JTAG AG28 AH28 AF28 AH27 AH21 DFT ...

Page 18

... Supply — SV — DD — XV — DD — S2V — DD — X2V — DD — V — DD_CORE — V — DD_PLAT — AV 20,28 DD_CORE — DD_PLAT — DD_DDR — DD_LBIU — DD_PCI1 — DD_SRDS — DD_SRDS2 — DD_CORE — DD_PLAT — — — Freescale Semiconductor ...

Page 19

... PLL test point analog SD2_IMP_CAL_RX Rx impedance calibration SD2_IMP_CAL_TX Tx impedance calibration SD2_PLL_TPA PLL test point analog Reserved Reserved NC MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Signal Name Package Pin Number M20,M24,N22,P21, R23,T21,U22,V20, W23, Y21 M28,N26,P24,P27, R25,T28,U24,U26,V24, W25,Y28,AA24,AA26, AB24,AB27,AD28 R12,M10,N11,L12 ...

Page 20

... MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev Signal Name Package Pin Number Ratio.” Section 22.3, “e500 Core PLL Ratio.” /V /GND planes internally and may be used by the core power supply to DD_CORE DD_PLAT . DD Power Pin Type Supply . DD Freescale Semiconductor Notes ...

Page 21

... PLL core supply voltage PLL other supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers and PCI Express MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Signal Name Package Pin Number Table 2. Absolute Maximum Ratings Symbol ...

Page 22

... DD 0 –55 to 150 C Specifications,” for details on Figure 2. Table 2 are the recommended Recommended Value Unit Notes 1.0 ± 1.1 ± 1.0 ± 1.0 ± 1.1 ± 1.0 ± 1.0 ± Freescale Semiconductor — — — 3 — 3 — 3 — 1 — 1,2 2 — ...

Page 23

... Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum during power-on reset and power-down sequences. 5. Caution: L/TV must not exceed L/TV IN power-on reset and power-down sequences. 6. Minimum temperature is specified with T MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol (eTSEC1) (eTSEC3 USB, eSDHC and JTAG signals ...

Page 24

... DD DD GND Not to Exceed 10 references SYSCLK. CLOCK references MCLK. CLOCK references EC_GTX_CLK125. CLOCK references LCLK. CLOCK references PCI1_CLK or SYSCLK. CLOCK Table 2 n signal (nominally set to GV REF 1 CLOCK /OV / for actual recommended core voltage). Voltage and LV based receivers appropriate DD Freescale Semiconductor ...

Page 25

... During the Deep Sleep state, the VDD core supply is removed. But all other power supplies remain applied. Therefore, there is no requirement to apply the VDD core supply before any other power rails when the silicon waking from Deep Sleep. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 4. Output Drive Capability Programmable Output Impedance (Ω ...

Page 26

... Freescale Semiconductor 9 Notes 1 ...

Page 27

... Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) Maximum (A) 1333 533 Thermal (W) Typical (W) Doze (W) Nap (W) Sleep (W) Deep Sleep (W) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor V Junction Platfor Tempera 5 Core cy m ture (V) (V) (°C) 105 500 1.0 1.0 ...

Page 28

... Platform Power 7 7 mean Max mean Max — 7.1/6.1 — 5.0/4.0 — 5.9/4.9 — 5.0/4.0 3.0 1.7 2.2 3.3 1.5 2.1 1.1 2.1 1.5 2.1 1.1 2.1 1.1 1 0.6 1.2 ) and 65°C junction temperature for Industrial Tier is 105 C. Freescale Semiconductor 9 Notes ...

Page 29

... CCB clock. That is, minimum clock high time is 2 × t low time is 2 × There is no minimum RTC frequency; RTC may be grounded if not needed. CCB MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 6. SYSCLK AC Timing Specifications Table 2) with OV = 3.3 V ± 165 mV ...

Page 30

... DDRCLK 0 KHK DDRCLK — — Typical Max Unit 125 — MHz 8 — ns — ns 0.75 1.0 — Typical Max Unit Notes — 166 MHz — 15.15 ns 1.0 1.2 ns — — +/– 150 Section 2.23.4, Freescale Semiconductor Notes — — — 2 — ...

Page 31

... SYSCLK is the primary clock input for the MPC8536E. Table 11 provides the PLL lock times. Parameter/Condition PLL lock times Local bus PLL PCI bus lock time MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 11. PLL Lock Times Min Max — 100 — 50 — ...

Page 32

... DC variations as measured at the receiver ≤ ≤ OUT DD (typ Max Unit Notes 1 0.51 × 0. REF GV + 0.3 V — DD – 0.125 V — REF μ — mA — — mA — (typ Max Unit Notes 1.575 V 1 0.51 × — – 0.100 V — REF μ Freescale Semiconductor ...

Page 33

... Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions with GV Parameter AC input low voltage 667 <=533 AC input high voltage 667 <=533 MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor (type Symbol DIO = 1.8 V ± 0.090 V (for DDR2 MHz 1.5 V ± ...

Page 34

... Figure 8. DDR SDRAM Input Timing Diagram Max Unit MV – 0.175 V REF — V Min Max Unit — — ps –240 240 — –300 300 — –365 365 — .This can be determined DISKEW ) is the absolute value CISKEW D1 t DISKEW Freescale Semiconductor Notes — — Notes — — ...

Page 35

... MHz 400 MHz MDQ/MECC/MDM output hold with respect to MDQS 667 MHz 533 MHz 400 MHz MDQS preamble start MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3 Symbol Min t 3.0 MCK ...

Page 36

... MCK symbolizes DDR timing (DD) for the time t DDKLDX NOTE Table 19 assumed that the Clock Max Unit Notes 0.6 × MCK for memory clock reference MCK describes the DDR timing (DD) DDKHMH can be modified through control DDKHMH follows the DDKHMP Freescale Semiconductor ...

Page 37

... Figure 10 shows the DDR SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 10. DDR SDRAM Output Timing Diagram MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 9. Timing Diagram for tDDKHMH t MCK ...

Page 38

... Table 21. SPI AC Timing Specifications Symbol t NIKHOX t NIKHOX t NIKHOV t NIKHOV t NIKHOX2 Ω Min Max Unit 2.4 — V — 0.5 V — 0 –0.3 0.8 V μA — ± Min Max Unit 0.5 — ns 4.0 — — 6.0 ns — 7.4 0 — ns Freescale Semiconductor Note — — — ...

Page 39

... Output Signals: SPIMOSI (See Note) Output Signals: SPI_CS[0:3] (See Note) Note: The clock edge is selectable on SPI. Figure 13. SPI AC Timing in Master mode (Internal Clock) Diagram MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 2 Symbol t NIKHOV2 t NIIVKH t NIIXKH (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

Page 40

... OV symbol referenced in IN Table 23. DUART AC Timing Specifications Value CCB clock/1,048,576 CCB clock/ sampled 0 after the 1-to-0 transition of the start bit. th sample. Max Unit 0.8 V μA ±5 — V 0.4 V Table 1 and Table 2. Unit Notes baud 2 baud 2,3 — 4 Freescale Semiconductor ...

Page 41

... DD 3 The symbol this case, represents the LV IN MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Section 2.10, “Ethernet Management Interface Electrical Section 2.9.3, “SGMII Interface Electrical Symbol Min Max LV 3 ...

Page 42

... Section 2.4.6, “Platform to FIFO Restrictions.” Table 26 and Table 27. Symbol Min t 6.0 FIT t 45 FITH t — FITJ Max Unit Notes 1,2 2. 0.3 V — DD 0.40 V — + 0.3 V — DD 0.70 V — 1, 2,3 μ μA — Table 1 and Table 2. Typ Max Unit 8.0 100 — 250 ps Freescale Semiconductor ...

Page 43

... Timing diagrams for FIFO appear in . GTX_CLK t FITH TXD[7:0] TX_EN TX_ER Figure 14. FIFO Transmit AC Timing Diagram MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol t FITR t FITF 1 t FITDX Symbol ...

Page 44

... GTX symbolizes GMII transmit timing (GT) with respect GTKHDX represents the GMII(G) transmit (TX) clock. For rise and fall times, GTX t FIRR Min Typ Max Unit — 8.0 — ns 0.5 — 5.0 ns — — 1.0 ns — — 1.0 ns symbolizes GMII GTKHDV Freescale Semiconductor ...

Page 45

... For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). Figure 17 provides the AC test load for eTSEC. Output MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t GTX t t ...

Page 46

... Note that, in represents the MII(M) transmit (TX) clock. For rise and fall times, the latter MTX t GRXR Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 symbolizes MII MTKHDX Freescale Semiconductor Unit ...

Page 47

... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the MRX appropriate letter: R (rise (fall). Figure 20 provides the AC test load for eTSEC. Output MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t MTX t t MTXF ...

Page 48

... TTX symbolizes the TBI transmit timing (TT) with respect to the time from t t MRXR t MRDXKL Min Typ Max — 8.0 — 40 — 60 1.0 — 5.0 — — 1.0 — — 1.0 symbolizes the TBI TTKHDV (K) going high TTX Freescale Semiconductor Unit TTX ...

Page 49

... The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively. These two clock signals are also referred as PMA_RX_CLK[0:1]. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t ...

Page 50

... V ± Symbol t TRR t TRRH t TRRJ t TRRR t TRRF t TRRDV t TRRDX t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Table 34. Min Typ Max 7.5 8.0 8 — — 250 — — 1.0 — — 1.0 2.0 — — 1.0 — — Freescale Semiconductor Unit ...

Page 51

... Duty cycle may be stretched/shrunk during speed changes or while transition to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t transitioned between. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 24. ...

Page 52

... RGTH t SKRGT_TX TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT_RX RXD[4] RXD[9] RXDV RXERR Table 36. of 3.3 V ± 5 Symbol Min t 15.0 RMT t 35 RMTH t — RMTJ t RGT t SKRGT_TX t SKRGT_RX Typ Max Unit 20.0 25 — 250 ps Freescale Semiconductor ...

Page 53

... At recommended operating conditions with L/TV Parameter/Condition TSECn_RX_CLK clock period TSECn_RX_CLK duty cycle TSECn_RX_CLK peak-to-peak jitter Rise time TSECn_RX_CLK (20%–80%) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5 Symbol t RMTR ...

Page 54

... Valid Data t RMRDV Figure 28. RMII Receive AC Timing Diagram 1 Symbol Min Typ Max t 1.0 — 2.0 RMRF t 4.0 — — RMRDV t 2.0 — — RMRDX symbolizes MII receive MRDVKH clock reference (K) going MRX Ω RMRR t RMRDX Figure 68. Section 3.6, “Connection Freescale Semiconductor Unit ...

Page 55

... MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Min — ...

Page 56

... TX-DIFFp amplitude - power up default); =1.0V, no common mode offset variation DD-Typ Freescale Semiconductor Figure 30. Notes — — Equalization setting: 1.0x Equalization setting: 1.09x Equalization setting: 1.2x Equalization setting: 1.33x Equalization setting: 1.5x Equalization setting: 1.71x Equalization setting: 2. — ...

Page 57

... Figure 30. SGMII Transmitter DC Measurement Circuit Table 40. SGMII DC Receiver Electrical Characteristics Parameter Supply Voltage DC Input voltage range Input differential voltage LSTS = 0 LSTS = 1 MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management SD2_TXn 50 Ω SD_RXm Ω C ...

Page 58

... Min Typ JD — — JT — — UI 799.92 800 tfall 50 — — rise Max Unit Notes 100 175 100 mV 5 Ω 120 — Ω 35 — — Max Unit Notes 0.17 UI p-p — 0.35 UI p-p — 800. 120 ps — 120 ps — Freescale Semiconductor ...

Page 59

... V /2 RX_DIFFp-p-min 0 − RX_DIFFp-p-min − RX_DIFFp-p-max 0 Figure 31. SGMII Receiver Input Compliance Mask MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management = 1.0V ± 5%. DD Symbol Min JD 0.37 JDR 0.55 JSIN 0.1 JT 0.65 BER — ...

Page 60

... Figure 34 provides the data and command input timing diagram. TSEC_1588_CLK TSEC_1588_TRIG_IN Figure 34. eTSEC IEEE 1588 Input AC timing MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev T1588CLKOUT t T1588CLKOUTH t T1588OV is non-inverting. Otherwise count starting falling edge. T1588CLKOUT t T1588CLK t T1588CLKH t T1588TRIGH Freescale Semiconductor ...

Page 61

... EC_MDC (management data clock). The electrical characteristics for GMII, SGMII, RGMII, RMII, TBI and RTBI are specified in Section 2.9, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management” MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics Table 43. ...

Page 62

... MDCH t ( )-3 MDKHDX plb_clk t 5 MDDVKH Max Unit 3. 0 0.50 V — V 0.90 V μA 40 μA — Table 1 and Table 2. Typ Max Unit 2.5 8.3 MHz 400 1350 ns — — ns — ( )+3 ns plb_clk — — ns Freescale Semiconductor Notes 2 — — 3,5,6 — ...

Page 63

... EC_MDIO (Input) EC_MDIO (Output) Figure 35. MII Management Interface Timing Diagram 2.11 USB This section provides the AC and DC electrical specifications for the USB interface of the MPC8536E. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 1 Symbol Min t 0 MDDXKH t — ...

Page 64

... V OV – 0.2 — — 0.2 OL Table 1 and Table 2. Max Unit — ns — ns — — ns symbolizes usb timing (US) for USIXKH symbolizes USB USKHOX of the signal in question for 3 Ω Freescale Semiconductor Unit V V μ Notes 2-5 2-5 2-5 2-5 2-5 for inputs ...

Page 65

... USB0_CLK/USB1_CLK/DR_CLK Input Signals Output Signals: MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t USIVKH t t USKHOX USKHOV Figure 37. USB Signals USB t USIXKH 65 ...

Page 66

... IH V –0 — 2 GND – 0 this case, represents the BV symbol referenced 3.3 V DC. DD Min Max Unit 3.13 3.47 1 0.3 DD –0.3 0.8 μA — ±5 2.4 — — 0.4 Table 1. = 2.5 V DC. DD Max Unit 2. 0 0.7 V μA 10 – 0 0.4 V Table 1. Freescale Semiconductor ...

Page 67

... Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol Condition BV — ...

Page 68

... LBKH/ LBK t — 150 ps LBKSKEW t 1.9 — ns LBIVKH1 t 1.8 — ns LBIVKH2 t 1.1 — ns LBIXKH1 t 1.1 — ns LBIXKH2 t 1.5 — ns LBOTOT t — 2.4 ns LBKHOV1 t — 2.5 ns LBKHOV2 t — 2.4 ns LBKHOV3 t — 2.4 ns LBKHOV4 t 0.8 — ns LBKHOX1 Freescale Semiconductor Notes Notes 2 — — ...

Page 69

... Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Configuration Symbol — — — ...

Page 70

... LSYNC_IN for PLL enabled or internal local bus clock for PLL Figure 38. Local Bus AC Test Load = 50 Ω 1.8 V DC) (continued Min Max Unit t 0.9 — ns LBKHOX2 t — 2.6 ns LBKHOZ1 t — 2.6 ns LBKHOZ2 symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for is guaranteed LBOTOT Ω Freescale Semiconductor Notes ...

Page 71

... LCLK[n] to that used in PLL Enable Mode. In this mode, output signals are launched at the falling edge of the LCLK[n] and inputs signals are captured at the rising edge of LCLK[n] with the exception of LGTA/LUPWAIT (which is captured at the falling edge of the LCLK[n]). MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t LBIVKH1 t LBIVKH2 ...

Page 72

... LBOTOT LBKLOV4 t LBIVKH1 t LBIXKH1 t LBIXKL2 LBKLOZ1 t LBKLOX2 = 3 with PLL disabled Symbol Min Max t 12 — LBK LBKH/ LBK t 5.1 — LBIVKH1 t 4.2 — LBIVKL2 t -1.4 — LBIXKH1 t -2.0 — LBIXKL2 t 1.4 — LBOTOT t — 0.5 LBKLOV1 Freescale Semiconductor Unit Notes — ...

Page 73

... These timing parameters for PLL bypass mode are defined in the opposite direction of the PLL enabled output hold timing parameters. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor enhanced Local Bus Controller (eLBC) 1 Symbol ...

Page 74

... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 41. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4(PLL Enabled) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

Page 75

... Characteristic Symbol Input high voltage V Input low voltage V Input/Output leakage current I IN Output high voltage V MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) t LBKHOZ1 t LBKHOV1 t LBIVKH2 t LBIVKH1 t LBKHOZ1 t LBKHOV1 Table 3) Condition — ...

Page 76

... Unit — 0.125 * OVDD 0.2 — — DD — 0.3 — values found in Table 3. IN 44. Min Max Unit MHz 0 25/50 20/52 0 400 KHz 100 7/10 — ns 7/10 — ns — — ns 2.5 — ns – symbolizes eSDHC FHSKHOV Freescale Semiconductor Notes — Notes 4,5 5 ...

Page 77

... This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8536E. 2.15.1 JTAG DC Electrical Characteristics Table 57 provides the DC electrical characteristics for the JTAG interface. Table 57. JTAG DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor SHSCK VM = Midpoint Voltage ( ...

Page 78

... Note that, in general, the clock JTG Max Unit μA ±5 — V 0.4 V through Figure 48. Min Max Unit 0 33.3 MHz 30 — — — — — ns — — ns symbolizes JTAG JTDVKH clock reference JTG Freescale Semiconductor Notes — — — — ...

Page 79

... This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the MPC8536E. Note that the external cabled applications or long backplane applications (Gen1x & Gen2x) are not supported. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor = 50 Ω Z ...

Page 80

... MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev Table 59. Symbol Min Typical t 100 — CLK_REF t –350 0 CLK_TOL t /t — — CLK_RISE CLK_FALL CLK_DUTY t — — CLK_CJ t –50 — CLK_PJ Max Unit Notes 150 MHz 1 +350 ppm — — — 100 ps — +50 ps 2,3 Freescale Semiconductor ...

Page 81

... MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz RL SATA_TXDD11 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol Min Typical — 1.5 3.0 T 666.4333 666 ...

Page 82

... SATA_TXDJ — — SATA_TXTJ Max Units Notes — 0.18 UI 0.14 — 0.42 UI 0.32 Freescale Semiconductor ...

Page 83

... RX Differential pair impedance 1.5G Z SATA_RXDIFFIM RX Single-Ended impedance Z SATA_RXSEIM 1.5G DC Coupled Common Mode V dc_cm Voltage MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 80% 80% t SATA_20-80TXfall TX+ TX- EARLY (TX+ is early) Min Typical Max 240 400 600 240 — 750 100 — ...

Page 84

... Units Notes — UI — UI Freescale Semiconductor ...

Page 85

... DC electrical characteristics for the I At recommended operating conditions with OV Parameter Supply voltage 3.3 V Input high voltage level Input low voltage level Low level output voltage MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol Min V 50 SATA_OOBDETE 75 T 646 ...

Page 86

... Freescale Semiconductor Notes 2 3 — Notes — — — — — — — ...

Page 87

... LOW period (t I2DVKH capacitance of one bus line in pF. B Figure 51 provides the AC test load for the I Output MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Electrical Specifications (continued) Table 63). 1 Symbol t I2KHDX ...

Page 88

... I2SXKL t t I2CH I2SVKH t t I2DXKL, I2OVKL Sr 2 Figure 52 Bus AC Timing Diagram Symbol this case, represents the OV symbol referenced I2KHKL I2CF t I2CR t I2PVKH P Min Max Unit 0 – 0.3 0.8 V μA — ±5 2.4 — V — 0.4 V Table 1 and Table 2. Freescale Semiconductor S ...

Page 89

... OL Notes: 1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications . 2. Note that the symbol this case, represents the OV IN MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol t PIWID t GTOWID PIWID = 50 Ω ...

Page 90

... Figure 54. PCI AC Test Load Min Max Unit Notes — 6.0 ns 2.0 — ns — 3.0 — — ns — clocks SYS — clocks 0.6 2.1 ns 0.6 2.1 ns (first two letters of functional for outputs. For symbolizes PCRHFV of the signal Ω Freescale Semiconductor — — ...

Page 91

... Volts. This is also referred as each signal wire’s Single-Ended Swing. 2. Differential Output Voltage, V The Differential Output Voltage (or Swing) of the transmitter, V voltages Differential Input Voltage, V MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor t PCIVKH CLK t PCKHOV t PCKHOZ ...

Page 92

... Differential Swing Differential Peak Voltage, V Differential Peak-Peak Voltage 500 mV in one phase and –500 mV in the other phase. The peak differential voltage ) is 1000 mV p-p. DIFFp-p = 2*V DIFFp cm_out SDn_TX SDn_TX – – B| DIFFp = 2*V (not shown) DIFFpp DIFFp Freescale Semiconductor = DIFFp TX-DIFFp ...

Page 93

... DC exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. SDn_REF_CLK SDn_REF_CLK Figure 58. Receiver of SerDes Reference Clocks MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor are specified in Table 2 and Table DD 50 Ω Input Amp 50 Ω ...

Page 94

... SD n _REF_CLK Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev Figure 60 shows the SerDes reference clock input requirement for Figure 61 100 mV < Vcm < 400 mV shows the SerDes Vmax < 800 mV Vmin > Freescale Semiconductor ...

Page 95

... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits ...

Page 96

... MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev _REF_CLK 100 Ω differential PWB trace SD n _REF_CLK Clock driver vendor dependent source termination resistor SD n _REF_CLK 100 Ω differential PWB trace SD n _REF_CLK 50 Ω SerDes Refer. CLK Receiver 50 Ω MPC8536E 50 Ω SerDes Refer. CLK Receiver 50 Ω Freescale Semiconductor ...

Page 97

... Single-Ended CLK Driver Chip 33 Ω Clock Driver CLK_Out Figure 65. Single-Ended Connection (Reference Only) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Figure 64 assumes that the LVPECL clock driver’s output impedance is SDn_REF_CLK 10nF R2 100 Ω differential PWB trace ...

Page 98

... Figure 66. Differential Measurement Points for Rise and Fall Time MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev 1.0V ± 5%. DD_SRDS1 DD_SRDS2 Symbol Rise Edge Rate Fall Edge Rate Rise-Fall Matching Figure 66. Figure 67. Min Max Unit Notes 1.0 4.0 V/ 1.0 4.0 V/ +200 — — –200 mV 2 — Freescale Semiconductor ...

Page 99

... Section 2.16, “Serial ATA (SATA)” Please note that external AC Coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor SD n _REF_CLK SD n _REF_CLK Clocks” ...

Page 100

... Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. 0.8 — 1 TX-DIFFp-p Min Typical Max Units — 10 — ns — — 100 ps –50 — Comments = 2*|V – See Note 2. TX-D+ TX-D- Freescale Semiconductor Notes 1 — 1,2,3 ...

Page 101

Table 71. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter V De- Emphasized TX-DE-RATIO Differential Output Voltage (Ratio) T Minimum TX Eye TX-EYE Width T Maximum time TX-EYE-MEDIAN-to- between the jitter MAX-JITTER median and maximum deviation from the median. T ...

Page 102

... Downstream and one Upstream Port. See Note 7. TX-EYE-MEDIAN-to-MAX-JITTER built-in. An external AC Coupling capacitor is required. TX Comments Figure 52 and measured over Figure 50) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 52). Note that the series Figure 52 for both V and V . TX-D+ TX-D- Freescale Semiconductor ...

Page 103

Transmitter Compliance Eye Diagrams The TX eye diagram in Figure 69 any real PCI Express interconnect + RX component. There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time ...

Page 104

... Required well as D– DC Impedance when the Receiver terminations do not have power. See Note 2*|V –V RX-IDLE-DET-DIFFp-p RX-D+ RX-D- Measured at the package pins of the Receiver An unexpected Electrical Idle (V RX-DIFFp must be recognized no RX-IDLE-DET-DIFFp-p longer than T RX-IDLE-DET-DIFF-ENTERING signal an unexpected idle condition. Freescale Semiconductor = |/2 | < to ...

Page 105

... A recovered calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Min Nom ...

Page 106

... Figure 71. Compliance Test/Measurement Load 2.23 Clocking This section describes the PLL configuration of the MPC8536E. Note that the platform clock is identical to the core complex bus (CCB) clock. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 106 NOTE Figure 71. NOTE Freescale Semiconductor ...

Page 107

... Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR data rate. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 74 Maximum Processor Core Frequency 800 MHz ...

Page 108

... LBCTL, LALE, LGPL2 Signals 4:1 100 9:2 101 Reserved 110 3:2 111 Table 77 CCB:SYSCLK Ratio 8:1 9:1 10:1 Reserved 12:1 Reserved Reserved Reserved 76. e500 core: CCB Clock Ratio 2:1 5:2 3:1 7:2 reflects the DDR data rate to DDRCLK ratio, Freescale Semiconductor ...

Page 109

... The use of PCI1_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of PCI1_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 77. DDR Clock Ratio Reset Configuration ...

Page 110

... MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 110 SYSCLK (MHz) 41.66 66.66 83 Platform /CCB Frequency (MHz) 333 333 415 400 500 333 533 333 417 400 500 533 × ( 527 MHz PCI Express link width ---------------------------------------------------------------------------------------------- 8 100 111 133.33 333 400 400 444 533 500 ) Freescale Semiconductor ...

Page 111

... Silicon Bump/Underfill (9.6 x 9.6 × 0.07 mm) Collapsed Thermal Resistance MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 79. Package Thermal Characteristics JEDEC Board Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — ...

Page 112

... Grid density lower than currently in the package library file will suffice for these simulations. The user will need to determine the optimal grid for their specific case. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 112 Value Solder and Air (29 × 29 × 0.5 mm) 0.034 0.034 12.1 Die Substrate Solder/air Units W/m•K A Freescale Semiconductor ...

Page 113

... Internal Package Conduction Resistance For the packaging technology, shown in • The die junction-to-case thermal resistance • The die junction-to-board thermal resistance MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Figure FC-PBGA Package Heat Sink Heat Sink Clip Die ...

Page 114

... DDR clock and DDRCLK is described in MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 114 Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Solder Spheres Radiation Convection Section 2.23.4, “DDR/DDRCLK PLL Ratio.” Section 2.23.3, Freescale Semiconductor ...

Page 115

... AV should be a filtered version • Signals on the SerDes interface are fed from the XV MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor _SRDS respectively). The AV level should always be equivalent through a low frequency filter scheme such as the following. DD Figure ...

Page 116

... MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 116 Table 1. See the MPC8536E PowerQUICC™ III Integrated Processor Reference , and LV as required. All unused active high inputs should and LV and GND pins of the device DD and XnV ) to ensure low jitter and XnV ) to the board DD DD Freescale Semiconductor , , , ...

Page 117

... OV P are designed to be close to each other in value. Then, Z Table 81 summarizes the signal impedance targets. The driver impedances are targeted at minimum V 105 ° C. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 2 C). /2 (see Figure DD /2. R then becomes the resistance of the pull-up devices ...

Page 118

... Target (cfg_pci_impd=1) 25 Target (cfg_pci_impd=0) 1. allows the COP port to independently assert HRESET or TRST, while ensuring that the DDR DRAM Symbol Unit 18 Target (full strength mode Target (full strength mode) 18 Target (full strength mode Target (full strength mode) Figure Freescale Semiconductor Ω Ω 78. ...

Page 119

... TRST should be tied to HRESET through Ω isolation resistor so that it is asserted when the system reset signal • (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations ...

Page 120

... COP_TRST 10 Ω 2 COP_VDD_SENSE NC COP_CHKSTP_OUT 10 kΩ COP_CHKSTP_IN COP_TMS COP_TDO COP_TDI COP_TCK Figure 78. JTAG Interface Connection kΩ 6 SRESET 1 10 kΩ HRESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST CKSTP_OUT 10 kΩ CKSTP_IN TMS TDO TDI TCK 10 kΩ Freescale Semiconductor ...

Page 121

... If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected (float) if not used: • SD1_TX[7:0] • SD1_TX[7:0] • Reserved pins: T22, T23 MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Guidelines for High-Speed Interface Termination 2 COP_TDO COP_TDI 3 4 ...

Page 122

... The following pins must be connected to X2GND if not used: • SD2_RX[1:0] • SD2_RX[1:0] 4 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Addressed by This Document.” MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 122 Section 4.1, “Part Numbers Fully Freescale Semiconductor ...

Page 123

... MMMMM is the 5-digit mask number. ATWLYYWW is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Part Numbers Fully Addressed by This Document Table 82. Device Nomenclature C ...

Page 124

... MPC8536EBVTAUL MPC8536CVTAUL MPC8536EBVTAVL MPC8536CVTAVL MPC8536E 29 mm × 783 1 mm 2.23 mm 2.8 mm 96.5Sn/3.5Ag 0.6 mm Notes MPC8536EAVTAKG MPC8536EAVTANG MPC8536EAVTAQG MPC8536EAVTATH MPC8536EAVTAUL MPC8536EAVTAVL Extended Temp Notes With Security MPC8536ECVTAKG MPC8536ECVTANG MPC8536ECVTAQG MPC8536ECVTATH MPC8536ECVTAUL MPC8536ECVTAVL FC-PBGA Freescale Semiconductor — — — — — — — ...

Page 125

... Caution must be taken not to short exposed metal capacitor pads on package top. 7. All dimensions are symmetric across the package center lines, unless dimensioned otherwise. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Mechanical Dimensions of the MPC8536E FC-PBGA NOTES for Figure 81 ...

Page 126

... Initial public release. MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 126 Table 85. Document Revision History Substantive Change(s) States,”updated the first sentence of the note to say, “The Figure 81, “Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8536E Freescale Semiconductor ...

Page 127

... MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Mechanical Dimensions of the MPC8536E FC-PBGA THIS PAGE INTENTIONALLY BLANK. 127 ...

Page 128

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...