MPC8536DS Freescale, MPC8536DS Datasheet - Page 119

• Manufacturer Part Number: MPC8536DS
• Manufacturer: Freescale

Specifications of MPC8536DS

• Lead Free Status / RoHS Status: Compliant

The COP interface has a standard header, shown in
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a
connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and
other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from
emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while
still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement
recommended in
3.10.1
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
Freescale Semiconductor
•
•
TRST should be tied to HRESET through a 0 k Ω isolation resistor so that it is asserted when the system reset signal
(HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale
recommends that the COP header be designed into the system as shown in
isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in
future debug situations.
No pull-up/pull-down is required for TDI, TMS, or TDO.
Termination of Unused Signals
Figure 79
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
is common to all known emulators.
Figure
79, for connection to the target system, and is based on the 0.025"
Figure
78. If this is not possible, the
JTAG Configuration Signals
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