EVAL-ADUC834QS Analog Devices Inc, EVAL-ADUC834QS Datasheet - Page 75

• Manufacturer Part Number: EVAL-ADUC834QS
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC834QS

• Lead Free Status / RoHS Status: Not Compliant

Parameter
SPI MASTER MODE TIMING (CPHA = 1)
*Characterized under the following conditions:
REV. A
Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 1.57 MHz, and
SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
t
t
t
t
t
t
t
t
t
DAV
DSU
DHD
DF
DR
SF
SL
SH
SR
SCLOCK Low Pulsewidth*
SCLOCK High Pulsewidth*
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MOSI
MISO
t
DOSU
t
DSU
MSB IN
Figure 75. SPI Master Mode Timing (CPHA = 1)
MSB
t
DHD
t
SH
t
DF
t
DAV
t
SL
t
DR
BITS 6–1
BITS 6–1
–75–
Min
100
100
Typ
630
630
10
10
10
10
LSB IN
t
SR
LSB
Max
50
25
25
25
25
t
SF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuC834
Figure
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