EVAL-ADUC834QS Analog Devices Inc, EVAL-ADUC834QS Datasheet - Page 17

• Manufacturer Part Number: EVAL-ADUC834QS
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC834QS

• Lead Free Status / RoHS Status: Not Compliant

ADC SFR INTERFACE
Both ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the
following pages.
ADCSTAT—(ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions
including reference detect and conversion overflow/underflow flags.
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
REV. A
ADCSTAT
ADCMODE
ADC0CON
ADC1CON
SF
ICON
Name
RDY0
RDY1
CAL
NOXREF
ERR0
ERR1
–––
–––
ADC Status Register. Holds general status of
the primary and auxiliary ADCs.
ADC Mode Register. Controls general modes
of operation for primary and auxiliary ADCs.
Primary ADC Control Register. Controls
specific configuration of primary ADC.
Auxiliary ADC Control Register. Controls
specific configuration of auxiliary ADC.
Sinc Filter Register. Configures the decimation
factor for the Sinc
and auxiliary ADC update rates.
Current Source Control Register. Allows
user control of the various on-chip current
source options.
3
Ready Bit for auxiliary ADC. Same definition as RDY0 referred to the auxiliary ADC.
No External Reference Bit (only active if primary or auxiliary ADC is active).
D8H
00H
Yes
Description
Ready Bit for primary ADC.
Set by hardware on completion of ADC conversion or calibration cycle.
Cleared directly by the user or indirectly by write to the mode bits to start another primary
ADC conversion or calibration. The primary ADC is inhibited from writing further results to its
data or calibration registers until the RDY0 bit is cleared.
Calibration Status Bit.
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below
a specified threshold. When Set, conversion results are clamped to all ones, if using external
reference.
Cleared to indicate valid V
Primary ADC Error Bit.
Set by hardware to indicate that the result written to the primary ADC data registers has
been clamped to all zeros or all ones. After a calibration, this bit also flags error conditions that
caused the calibration registers not to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.
Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC.
Reserved for Future Use
Reserved for Future Use
filter and thus the primary
Table IV. ADCSTAT SFR Bit Designations
REF
–17–
.
ADC0L/M/H
ADC1L/H
OF0L/M/H
OF1L/H
GN0L/M/H
GN1L/H
Primary ADC 24-bit conversion result is held
in these three 8-bit registers.
Auxiliary ADC 16-bit conversion result is held
in these two 8-bit registers.
Primary ADC 24-bit Offset Calibration
Coefficient is held in these three 8-bit registers.
Auxiliary ADC 16-bit Offset Calibration
Coefficient is held in these two 8-bit registers.
Primary ADC 24-bit Gain Calibration
Coefficient is held in these three 8-bit registers.
Auxiliary ADC 16-bit Gain Calibration
Coefficient is held in these two 8-bit registers.
ADuC834