EVAL-ADUC834QS Analog Devices Inc, EVAL-ADUC834QS Datasheet - Page 74

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EVAL-ADUC834QS

Manufacturer Part Number
EVAL-ADUC834QS
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADUC834QS

Lead Free Status / RoHS Status
Not Compliant
ADuC834
Parameter
UART TIMING (Shift Register Mode)
t
t
t
t
t
XLXL
QVXH
DVXH
XHDX
XHQX
Serial Port Clock Cycle Time
Output Data Setup to Clock
Input Data Setup to Clock
Input Data Hold after Clock
Output Data Hold after Clock
(OUTPUT CLOCK)
(OUTPUT DATA)
(INPUT DATA)
ALE (O)
RxD
RxD
TxD
Figure 74. UART Timing in Shift Register Mode
MSB
01
MSB
Min
12.58 MHz Core_Clk
662
292
0
42
t
DVXH
t
BIT 6
QVXH
67
Typ
0.95
BIT 6
–74–
t
t
XHQX
XHDX
Max
Min
10t
2t
0
2t
CORE
CORE
CORE
Variable Core_Clk
+ 133
– 117
BIT 1
– 133
BIT 1
t
XLXL
Typ
12t
CORE
SET RI
SET TI
LSB
OR
Max
Unit
ns
ns
ns
ns
s
REV. A
Figure
74
74
74
74
74