XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 195

• Manufacturer Part Number: XC5VLX330-2FFG1760C
• Description: FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX330-2FFG1760C

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 331776
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 1200
• Ram Bits: 10616832
• Number Of Logic Elements/cells: 331776
• Number Of Labs/clbs: 25920
• Total Ram Bits: 10616832
• Number Of I /o: 1200
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Multiplexers
delay to access the LUT. This operation is asynchronous and independent of the clock and
clock-enable signals.
Static Read Operation
If the 5-bit address is fixed, the Q output always uses the same bit position. This mode
implements any shift-register length from 1 to 32 bits in one LUT. The shift register length
is (N+1), where N is the input address (0 – 31).
The Q output changes synchronously with each shift operation. The previous bit is shifted
to the next position and appears on the Q output.
Shift Register Summary
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Function generators and associated multiplexers in Virtex-5 FPGAs can implement the
following:
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These wide input multiplexers are implemented in one level or logic (or LUT) using the
dedicated F7AMUX, F7BMUX, and F8MUX multiplexers. These multiplexers allow LUT
combinations of up to four LUTs in a slice.
A shift operation requires one clock edge.
Dynamic-length read operations are asynchronous (Q output).
Static-length read operations are synchronous (Q output).
The data input has a setup-to-clock timing specification.
In a cascadable configuration, the Q31 output always contains the last bit value.
The Q31 output changes synchronously after each shift operation.
4:1 multiplexers using one LUT
8:1 multiplexers using two LUTs
16:1 multiplexers using four LUTs
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CLB Overview
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