XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 110

• Manufacturer Part Number: XC5VLX330-2FFG1760C
• Description: FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX330-2FFG1760C

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 331776
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 1200
• Ram Bits: 10616832
• Number Of Logic Elements/cells: 331776
• Number Of Labs/clbs: 25920
• Total Ram Bits: 10616832
• Number Of I /o: 1200
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Phase-Locked Loops (PLLs)
110
PLL Application Example
The following PLL attribute settings result in a wide variety of synthesized clocks:
Figure 3-16
X-Ref Target - Figure 3-16
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
VCOCLK
REFCLK
CLKOUT0_PHASE = 0;
CLKOUT0_DUTY_CYCLE = 0.5;
CLKOUT0_DIVIDE = 2;
CLKOUT1_PHASE = 90;
CLKOUT1_DUTY_CYCLE = 0.5;
CLKOUT1_DIVIDE = 2;
CLKOUT2_PHASE = 0;
CLKOUT2_DUTY_CYCLE = 0.25;
CLKOUT2_DIVIDE = 4;
CLKOUT3_PHASE = 90;
CLKOUT3_DUTY_CYCLE = 0.5;
CLKOUT3_DIVIDE = 8;
CLKOUT4_PHASE = 0;
CLKOUT4_DUTY_CYCLE = 0.5;
CLKOUT4_DIVIDE = 8;
CLKOUT5_PHASE = 135;
CLKOUT5_DUTY_CYCLE = 0.5;
CLKOUT5_DIVIDE = 8;
CLKFBOUT_PHASE = 0;
CLKFBOUT_MULT = 8;
DIVCLK_DIVIDE = 1;
CLKIN1_PERIOD = 10.0;
displays the resulting waveforms.
www.xilinx.com
Figure 3-16: Example Waveform
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_3_19_032506