XC2V2000-4FGG676C Xilinx Inc, XC2V2000-4FGG676C Datasheet - Page 88
![FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC2V2000-4FGG676C
Manufacturer Part Number
XC2V2000-4FGG676C
Description
FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V2000-4FGG676C
Package
676FBGA
Family Name
Virtex-IIÂ
Device Logic Units
24192
Device System Gates
2000000
Number Of Registers
21504
Maximum Internal Frequency
650 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
456
Ram Bits
1032192
Number Of Labs/clbs
2688
Total Ram Bits
1032192
Number Of I /o
456
Number Of Gates
2000000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1351
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2V2000-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Table 47: Sample Window
Table 48: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. This parameter indicates the total sampling error of Virtex-II DDR input registers across voltage, temperature, and process. The
Notes:
1. IFF = Input Flip-Flop
2. The timing values were measured using the fine-phase adjustment feature of the DCM.
3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.
Sampling Error at Receiver Pins
Data Input Set-Up and Hold Times Relative to a Forwarded
Clock Input Pin, Using DCM and Global Clock Buffer.
For situations where clock and data inputs conform to
different standards, adjust the setup and hold values
accordingly using the values shown in
Characteristics Standard Adjustments, page
No Delay
Global Clock and IFF with DCM
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - T
- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree skew.
Description
R
Description
(1)
IOB Input Switching
DCD_CLK180
11.
Symbol
T
SAMP
www.xilinx.com
Symbol
T
T
PSDCM
Virtex-II Platform FPGAs: DC and Switching Characteristics
PHDCM
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
/
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
XC2V40
XC2V80
Device
500
500
500
500
500
500
500
500
500
500
-6
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
-6
Speed Grade
Speed Grade
500
500
500
500
500
500
500
500
500
500
500
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.6
0.2/0.6
0.2/0.6
-5
-5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.6
0.2/0.6
0.2/0.6
0.2/0.7
550
550
550
550
550
550
550
550
550
550
550
-4
-4
Module 3 of 4
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
40
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