XC2V2000-4FGG676C Xilinx Inc, XC2V2000-4FGG676C Datasheet - Page 69
![FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC2V2000-4FGG676C
Manufacturer Part Number
XC2V2000-4FGG676C
Description
FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V2000-4FGG676C
Package
676FBGA
Family Name
Virtex-IIÂ
Device Logic Units
24192
Device System Gates
2000000
Number Of Registers
21504
Maximum Internal Frequency
650 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
456
Ram Bits
1032192
Number Of Labs/clbs
2688
Total Ram Bits
1032192
Number Of I /o
456
Number Of Gates
2000000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1351
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2V2000-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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CLB Distributed RAM Switching Characteristics
Table 22: CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Table 23: CLB Shift Register Switching Characteristics
DS031-3 (v3.5) November 5, 2007
Product Specification
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Clock CLK
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Clock CLK
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
BX/BY data inputs (DIN)
F/G address inputs
SR input (WS)
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
Clock CLK to X/Y outputs
Clock CLK to X/Y outputs
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
Clock CLK to F5 output
BX/BY data inputs (DIN)
SR input (WS)
Minimum Pulse Width, High
Minimum Pulse Width, Low
R
Description
Description
www.xilinx.com
T
SRLDS
T
Symbol
WSS
T
T
T
T
T
T
Virtex-II Platform FPGAs: DC and Switching Characteristics
T
T
T
REGXB
REGYB
REGF5
REG32
T
T
T
CKSH
SRPH
Symbol
WES
SRPL
T
REG
T
SHCKOF5
SHCKO16
SHCKO32
/T
/T
DS
AS
T
T
T
WPH
WPL
SRLDH
WSH
WC
/T
/T
/T
AH
DH
WEH
0.53/–0.07
0.19/–0.06
0.53/–0.09
0.42/–0.01
0.40/ 0.00
2.31
2.65
2.23
2.18
1.92
2.45
0.57
0.57
1.63
1.97
1.77
0.57
0.57
1.14
-6
-6
Speed Grade
Speed Grade
0.58/–0.10
0.46/–0.01
0.58/–0.08
0.21/–0.07
0.44/ 0.00
1.79
2.17
1.94
0.63
0.63
1.25
2.54
2.92
2.46
2.40
2.11
2.69
0.63
0.63
-5
-5
0.67/–0.11
0.53/–0.01
0.67/–0.09
0.24/–0.08
0.50/ 0.00
2.05
2.49
2.23
0.72
0.72
1.44
2.92
3.35
2.82
2.75
2.43
3.09
0.72
0.72
-4
-4
Module 3 of 4
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
Units
Units
21
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