XC2V2000-4FGG676C Xilinx Inc, XC2V2000-4FGG676C Datasheet - Page 72
![FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC2V2000-4FGG676C
Manufacturer Part Number
XC2V2000-4FGG676C
Description
FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V2000-4FGG676C
Package
676FBGA
Family Name
Virtex-IIÂ
Device Logic Units
24192
Device System Gates
2000000
Number Of Registers
21504
Maximum Internal Frequency
650 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
456
Ram Bits
1032192
Number Of Labs/clbs
2688
Total Ram Bits
1032192
Number Of I /o
456
Number Of Gates
2000000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1351
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2V2000-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Enhanced Multiplier Switching Characteristics
Table 26
Virtex-II devices. For more information on stepping revisions, availability, and ordering instructions, see your local sales
representative.
Table 26: Enhanced Multiplier Switching Characteristics
DS031-3 (v3.5) November 5, 2007
Product Specification
Propagation Delay to Output Pin
Input to Pin 35
Input to Pin 34
Input to Pin 33
Input to Pin 32
Input to Pin 31
Input to Pin 30
Input to Pin 29
Input to Pin 28
Input to Pin 27
Input to Pin 26
Input to Pin 25
Input to Pin 24
Input to Pin 23
Input to Pin 22
Input to Pin 21
Input to Pin 20
Input to Pin 19
Input to Pin 18
Input to Pin 17
Input to Pin 16
Input to Pin 15
Input to Pin 14
Input to Pin 13
Input to Pin 12
Input to Pin 11
Input to Pin 10
Input to Pin 9
Input to Pin 8
Input to Pin 7
Input to Pin 6
Input to Pin 5
Input to Pin 4
Input to Pin 3
Input to Pin 2
Input to Pin 1
Input to Pin 0
and
R
Table 27
provide timing information for enhanced Virtex-II multiplier blocks, available in stepping revisions of
Description
www.xilinx.com
Virtex-II Platform FPGAs: DC and Switching Characteristics
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
MULT1_P35
MULT1_P34
MULT1_P33
MULT1_P32
MULT1_P31
MULT1_P30
MULT1_P29
MULT1_P28
MULT1_P27
MULT1_P26
MULT1_P25
MULT1_P24
MULT1_P23
MULT1_P22
MULT1_P21
MULT1_P20
MULT1_P19
MULT1_P18
MULT1_P17
MULT1_P16
MULT1_P15
MULT1_P14
MULT1_P13
MULT1_P12
MULT1_P11
MULT1_P10
Symbol
MULT1_P9
MULT1_P8
MULT1_P7
MULT1_P6
MULT1_P5
MULT1_P4
MULT1_P3
MULT1_P2
MULT1_P1
MULT1_P0
4.66
4.57
4.47
4.37
4.28
4.18
4.08
3.99
3.89
3.79
3.69
3.60
3.50
3.40
3.31
3.21
3.11
3.02
2.92
2.82
2.72
2.63
2.53
2.43
2.34
2.24
2.14
2.05
1.95
1.85
1.75
1.66
1.56
1.46
1.37
1.27
-6
Speed Grade
5.14
5.03
4.93
4.82
4.71
4.61
4.50
4.39
4.28
4.18
4.07
3.96
3.86
3.75
3.64
3.54
3.43
3.32
3.21
3.11
3.00
2.89
2.79
2.68
2.57
2.47
2.36
2.25
2.14
2.04
1.93
1.82
1.72
1.61
1.50
1.40
-5
5.91
5.79
5.66
5.54
5.42
5.29
5.17
5.05
4.92
4.80
4.68
4.56
4.43
4.31
4.19
4.06
3.94
3.82
3.69
3.57
3.45
3.33
3.20
3.08
2.96
2.83
2.71
2.59
2.46
2.34
2.22
2.10
1.97
1.85
1.73
1.60
-4
Module 3 of 4
ns, Max
ns, Max
ns, Max
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ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
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ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Units
24
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