ATTINY12L-4PU Atmel, ATTINY12L-4PU Datasheet - Page 26

• Manufacturer Part Number: ATTINY12L-4PU
• Description: MCU 8-Bit ATtiny AVR RISC 1KB Flash 3.3V/5V 8-Pin PDIP
• Manufacturer: Atmel

Specifications of ATTINY12L-4PU

• Package: 8PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 4 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 6
• Interface Type: SPI
• Number Of Timers: 1
• Program Memory Size: 1 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Processor Series: ATTINY1x
• Core: AVR8
• Maximum Clock Frequency: 4 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details

Power-on Reset for the
ATtiny12
26
ATtiny11/12
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-
tion level is nominally 1.4V. The POR is activated whenever V
level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail-
ure in supply voltage.
The Power-on Reset (POR) circuit ensures that the device is reset from power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-
mines the delay for which the device is kept in Reset after V
of the delay counter can be defined by the user through the CKSEL fuses. The different
selections for the delay period are presented in Table 10. The Reset signal is activated
again, without any delay, when the V
If the built-in start-up delay is sufficient, RESET can be connected to V
an external pull-up resistor. See Figure 17. By holding the RESET pin low for a period
after V
ure 18 for a timing example on this.
Figure 17. MCU Start-up, RESET Tied to V
Figure 18. MCU Start-up, RESET Extended Externally
INTERNAL
TIME-OUT
INTERNAL
TIME-OUT
RESET
RESET
RESET
RESET
V
V
CC
CC
CC
has been applied, the Power-on Reset period can be extended. Refer to Fig-
V
V
V
POT
RST
POT
t
TOUT
CC
decreases below detection level.
V
RST
CC
.
t
TOUT
CC
CC
rise. The time-out period
is below the detection
CC
directly or via
1006F–AVR–06/07