72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 37

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. t
2. LD = HIGH.
3. First data word latency = t
4. OE is LOW.
Q0 - Qn
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
WCLK
RCLK
rising edge of WCLK and the rising edge of RCLK is less than t
WEN
SKEW1
RCS
REN
Dn
EF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
t
ENS
ENS
t
RCSLZ
t
ENH
SKEW1
t
A
+ 1*T
LAST DATA-1
RCLK
Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)
+ t
REF.
t
RCSHZ
SKEW1
t
ENS
, then EF deassertion may be delayed one extra RCLK cycle.
t
RCSLZ
t
REF
t
37
A
t
t
ENS
DS
LAST DATA
D
t
ENS
x
t
SKEW1
t
ENH
2Kx18/4Kx9, 4Kx18/
t
DH
(1)
1
t
RCSHZ
COMMERCIAL AND INDUSTRIAL
2
TEMPERATURE RANGES
t
REF
REF
FEBRUARY 10, 2009
). If the time between the
5909 drw 17