72T1875L5BBI Integrated Device Technology (Idt), 72T1875L5BBI Datasheet - Page 30

• Manufacturer Part Number: 72T1875L5BBI
• Description: FIFO Mem Async/Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 144-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T1875L5BBI

• Package: 144BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 288 Kb
• Organization: 16Kx18|32Kx9
• Data Bus Width: 9/18 Bit
• Timing Type: Asynchronous|Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: -40 to 85 °C

JTAG INTERFACE
support the JTAG boundary scan interface. The IDT72T1845/72T1855/
72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/72T18125 in-
corporates the necessary tap controller and modified pad cells to implement the
JTAG facility.
program files for these devices.
TEST ACCESS PORT (TAP)
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
Note that IDT provides appropriate Boundary Scan Description Language
The Tap interface is a general-purpose port that provides access to the
TDO
TDI
TMS
TCLK
TRST
T
A
P
Cont-
roller
TAP
Figure 7. Boundary Scan Architecture
clkDR, ShiftDR
clklR, ShiftlR
UpdatelR
UpdateDR
Instruction Register
30
Control Signals
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE TAP CONTROLLER
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
The Standard JTAG interface consists of four basic elements:
•
•
•
•
The following sections provide a brief description of each element. For a
The Figure below shows the standard Boundary-Scan Architecture.
The Tap controller is a synchronous finite state machine that responds to
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
2Kx18/4Kx9, 4Kx18/
Instruction Decode
Mux
5909 drw11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009