MT48H8M16LFB4-75 IT:K Micron Technology Inc, MT48H8M16LFB4-75 IT:K Datasheet - Page 44

• Manufacturer Part Number: MT48H8M16LFB4-75 IT:K
• Description: DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 1.8V 54-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75 IT:K

• Package: 54VFBGA
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 8|5.4 ns
• Operating Temperature: -40 to 85 °C
• Organization: 8Mx16
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Extended Mode Register
Figure 15: Extended Mode Register Definition
Temperature-Compensated Self Refresh
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
En + 2
0
0
1
1
En + 1
0
1
0
1
En
0
–
...
0
–
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
E10
0
Note:
–
E9
0
–
The extended mode register (EMR) controls additional functions beyond those control-
led by the mode register. These additional functions include TCSR, PASR, and output
drive strength.
The EMR is programmed via the LMR command (BA1 = 1, BA0 = 0) and retains the stor-
ed information until it is programmed again or the device loses power.
The EMR must be programmed with E[n:7] set to 0. It must be loaded when all banks
are idle and no bursts are in progress, and the controller must wait the specified time
before initiating any subsequent operation. Violating either of these requirements re-
sults in unspecified operation. After the values are entered, the EMR settings are re-
tained even after exiting deep power-down mode.
This device includes a temperature sensor that is implemented for automatic control of
the self refresh oscillator. Programming the temperature-compensated self refresh
(TCSR) bits has no effect on the device. The self refresh oscillator will continue refresh
at the optimal factory-programmed rate for the device temperature.
n + 2
1
BA1
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
E8
0
–
n + 1
0
BA0
E7–E0
Valid
–
An
n
...
Normal AR operation
All other states reserved
Operation
...
10
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E7
9
0
0
0
0
1
1
1
1
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
E6
8
0
0
1
1
0
0
1
1
44
E5
7
0
1
0
1
0
1
0
1
DS
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
5
E2
0
0
0
0
1
1
1
1
TCSR
4
E1
0
0
1
1
0
0
1
1
1
3
E0
0
1
0
1
0
1
0
1
2
PASR
Partial-Array Self Refresh Coverage
Full array
1/2 array
1/4 array
Reserved
Reserved
1/8 array
1/16 array
Reserved
Extended Mode Register
1
0
©2008 Micron Technology, Inc. All rights reserved.
Address bus
Extended mode
register (Ex)