MT47H64M8CF-25E IT:G Micron Technology Inc, MT47H64M8CF-25E IT:G Datasheet - Page 42

• Manufacturer Part Number: MT47H64M8CF-25E IT:G
• Description: 64MX8 DDR2 SDRAM PLASTIC IND TEMP FBGA 1.8V
• Manufacturer: Micron Technology Inc

45. The half-clock of
46. ODT turn-on time
47. ODT turn-off time
48. Half-clock output parameters must be derated by the actual
49. The -187E maximum limit is 2 ×
50. Should use 8
51. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row ad-
amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53,
0.03, or 2.47, for
on time
is when the bus is in High-Z. Both are measured from
this will result in each parameter becoming larger. The parameter
tracting both
ing both
future.
dress may result in reduction of the product lifetime.
t
AON (MAX) is when the ODT resistance is fully on. Both are measured from
t
ERR
t
5per
t
CK for backward compatibility.
ERR
t
t
(MIN) and
AOF (MIN) and 2.5 + 0.03, or 2.53, for
AOFD’s 2.5
t
5per
t
AON (MIN) is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-
AOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time
(MAX) and
t
JITdty (MIN).
t
CK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the
t
CK +
t
JITdty (MAX). The parameter
t
AC (MAX) + 1000 but it will likely be 3 x
t
AOFD.
t
AOF (MAX).
t
ERR
t
AOF (MAX) is required to be derated by subtract-
5per
t
AOF (MIN) is required to be derated by sub-
and
t
JITdty when input clock jitter is present;
t
CK +
t
t
t
AC (MAX) + 1000 in the
AOFD would actually be 2.5 -
AOND.
t
AOF (MAX)