SI5326C-C-GM Silicon Laboratories Inc, SI5326C-C-GM Datasheet - Page 6

DSPLL 36-Pin QFN EP

SI5326C-C-GM

Manufacturer Part Number
SI5326C-C-GM
Description
DSPLL 36-Pin QFN EP
Manufacturer
Silicon Laboratories Inc
Type
Jitter Attenuatorr
Datasheet

Specifications of SI5326C-C-GM

Package
36QFN EP
Operating Temperature
-40 to 85 °C
Pll
Yes
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
Yes/Yes
Frequency - Max
346MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
1.71 V ~ 3.63 V
Mounting Type
Surface Mount
Package / Case
36-QFN
Frequency-max
346MHz
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
QFN EP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1746
336-1746-5
336-1746

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5326C-C-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
SI5326C-C-GMR
Quantity:
1 507
Si5326
6
Table 2. DC Characteristics (Continued)
(V
Differential Output
Swing
Single Ended Output
Swing
Differential Output
Voltage
Common Mode Output
Voltage
Differential Output
Voltage
Common Mode Output
Voltage
Differential Output
Resistance
Output Voltage Low
Output Voltage High
Notes:
DD
1.
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal V
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
Parameter
Current draw is independent of supply voltage
Family Reference Manual for more details.
CKO
CKO
CKO
CKO
CKO
Symbol
CKO
CKO
CKO
CKO
VOHLH
VOLLH
VCM
VCM
VSE
VD
VD
VD
RD
LVPECL 100  load line-
LVPECL 100  load line-
LVDS 100 load line-to-
CML 100  load line-to-
CML 100  load line-to-
A
100  load line-to-line
100  load line-to-line
CML, LVPECL, LVDS
= –40 to 85 °C)
DD
Low Swing LVDS
Test Condition
≥ 2.5 V.
V
DD
CMOS
CMOS
to-line
to-line
LVDS
line
line
line
= 1.71 V
Rev. 1.0
1.125
0.8 x
V
Min
350
500
350
1.1
0.5
DD
V
DD
Typ
425
700
425
200
1.2
-0.36
1.275
Max
0.93
500
900
500
1.9
0.4
mV
mV
mV
Unit
V
V
V
V
V
V
PP
PP
PP
PP
PP

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