74LVC1G17GW-G NXP Semiconductors, 74LVC1G17GW-G Datasheet - Page 3

no-image

74LVC1G17GW-G

Manufacturer Part Number
74LVC1G17GW-G
Description
Schmitt Trigger Buffer 1-CH Non-Inverting CMOS 5-Pin TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC1G17GW-G

Package
5TSSOP
Logic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number Of Outputs Per Chip
1
Input Signal Type
Single-Ended
Maximum Propagation Delay Time @ Maximum Cl
3.2(Typ)@2.7V|3(Typ)@3.3V|2.2(Typ)@5V ns
Tolerant I/os
5 V
Typical Quiescent Current
0.1 uA
Polarity
Non-Inverting
NXP Semiconductors
6. Pinning information
Table 3.
7. Functional description
Table 4.
[1]
74LVC1G17
Product data sheet
Symbol
n.c.
A
GND
Y
V
Input
A
L
H
Fig 4.
CC
H = HIGH voltage level; L = LOW voltage level
GND
n.c.
A
Pin configuration
SOT353-1 and SOT753
Pin description
Function table
1
2
3
74LVC1G17
6.1 Pinning
6.2 Pin description
001aaf190
3
Pin
SOT353-1, SOT753
1
2
4
5
[1]
5
4
V
Y
CC
All information provided in this document is subject to legal disclaimers.
Fig 5.
3
SOT886, SOT891, SOT1115, SOT1202
1, 5
2
4
6
Rev. 7 — 10 November 2010
GND
n.c.
Pin configuration SOT886
A
Transparent top view
74LVC1G17
1
2
3
Output
Y
L
H
001aaf191
6
5
4
V
n.c.
Y
CC
Fig 6.
Single Schmitt trigger buffer
Description
not connected
data input
ground (0 V)
data output
supply voltage
GND
n.c.
Pin configuration SOT891,
SOT1115 and SOT1202
A
Transparent top view
74LVC1G17
74LVC1G17
1
2
3
© NXP B.V. 2010. All rights reserved.
001aaf402
6
5
4
V
n.c.
Y
CC
3 of 19

Related parts for 74LVC1G17GW-G