74LVC1G17GW-G NXP Semiconductors, 74LVC1G17GW-G Datasheet - Page 14

no-image

74LVC1G17GW-G

Manufacturer Part Number
74LVC1G17GW-G
Description
Schmitt Trigger Buffer 1-CH Non-Inverting CMOS 5-Pin TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC1G17GW-G

Package
5TSSOP
Logic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number Of Outputs Per Chip
1
Input Signal Type
Single-Ended
Maximum Propagation Delay Time @ Maximum Cl
3.2(Typ)@2.7V|3(Typ)@3.3V|2.2(Typ)@5V ns
Tolerant I/os
5 V
Typical Quiescent Current
0.1 uA
Polarity
Non-Inverting
NXP Semiconductors
Fig 17. Package outline SOT1115 (XSON6)
74LVC1G17
Product data sheet
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
mm
SOT1115
Unit
Outline
version
max
nom
min
0.35 0.04
A
(1)
A
1
0.20
0.15
0.12
b
IEC
0.95
0.90
0.85
terminal 1
index area
D
e
(6×)
1.05
1.00
0.95
L
(2)
E
1
0.55
JEDEC
e
All information provided in this document is subject to legal disclaimers.
1
6
0.3
e
e
1
1
References
Rev. 7 — 10 November 2010
D
2
5
0.35
0.30
0.27
0
L
e
1
0.40
0.35
0.32
L
b
3
4
1
JEITA
scale
0.5
A
L
E
1
A
1 mm
(4×)
(2)
Single Schmitt trigger buffer
European
projection
74LVC1G17
© NXP B.V. 2010. All rights reserved.
Issue date
10-04-02
10-04-07
sot1115_po
SOT1115
14 of 19

Related parts for 74LVC1G17GW-G