AT84CS001VTPY E2V, AT84CS001VTPY Datasheet - Page 3

• Manufacturer Part Number: AT84CS001VTPY
• Description: Demultiplexer 240-Pin EBGA
• Manufacturer: E2V

Specifications of AT84CS001VTPY

• Package: 240EBGA
• Power Supply Type: Analog|Digital
• Typical Supply Current: 600 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 2.375|3.15 V
• Maximum Operating Supply Voltage: 2.625|3.45 V

2. Overview
e2v semiconductors SAS 2009
The AT84CS001 is a monolithic high-speed demultiplexer (DMUX) using high-speed e2v technology.
It enables the user to lower a 10-bit stream of 2.2 Gsps maximum by a factor of two or four. One can
obtain a 1:8 ratio by using two interleaved AT84CS001 devices. The maximum input data rate is 2.2
Gsps in 1:4 ratio and 1.8 Gsps in 1:2 ratio.
The AT84CS001 DMUX is capable of processing an 11-bit data flow. The additional 11
might be connected for example to the out-of-range bit of a 10-bit ADC.
The input and output clocks as well as the input and output data are LVDS compatible. Digital inputs are
100Ω differentially terminated on chip. Digital output buffers shall be terminated by a 100Ω differential
ASIC load.
The improved architecture of the DMUX facilitates interfacing with high-speed ADCs operating at up to
2.2 Gsps. A tunable delay cell is integrated in serial with the clock input: it can be used to tune the delay
between the data and clock paths namely for high speed rates and in the case of misalignment or skews
between the external clock path and the data path. The delay is controlled by means of the CLKDACTRL
analog control input. The tunable delay ranges from -250 ps to 250 ps for CLKDACTRL varying from
V
Two modes can be selected for the clock input (CLK and CLK/2) and the clock output (DR and DR/2):
The data outputs can be received at the DMUX output in two different modes:
The AT84CS001 DMUX is started by the ASYNCRST control input that acts as a master asynchronous
reset for the device. Once reset, there is no loss of synchronization over an indefinite time period, there-
fore no additional incoming synchronous reset signal is required.
The power consumption of the AT84CS001 is 2.7W and can be reduced by approximately 60% of its
nominal value by means of the SLEEP control input.
A standalone delay cell is provided. It features a typical 550 ps tuning range (± 275 ps around the center
value of DACTRL analog control input).
A Built-in Self Test (BIST) is implemented for rapid debugging of the DMUX.
The AT84CS001 DMUX is a companion chip designed to fit perfectly with all of e2v’s high-speed ADCs.
CCD
• CLK and DR mode: Only the rising edges of the input (CLK,CLKN) and output (DR, DRN) clocks are
• CLK/2 and DR/2 mode: Both the rising and falling edges of the input (CLK,CLKN) and output (DR,
• Staggered: even and odd bits are output with half a data period delay
• Simultaneous: even and odd bits are output at the same time
active. The input (or output) clock rate remains the same as the input or output data rate.
DRN) clocks are active. The input (or output) clock rate is half the input or output data rate.
/2 to (2 × V
CCD
)/3.
0809E–BDC–05/09
AT84CS001
th
bit (IOR, IORN)
3