STV2310D STMicroelectronics, STV2310D Datasheet - Page 98

• Manufacturer Part Number: STV2310D
• Description: Video ICs Digital Video Decodr
• Manufacturer: STMicroelectronics
• Type: High Quality front end videor

Specifications of STV2310D

• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register List
98/113
Address (hex): 81h - Read Only
Reset Value (bin): Undefined
VLOCK
HLOCK
PLLLOCK
5060ID
TVSTDID
TVSTD[2:0]
Address (hex): 82h - Read Only
Reset Value (bin): Undefined
VSYNCLOC_
NSTD
BLANKLVL_SHIF
T_DETECTED
INTERLACED_
DETECTED
DVD_DETECTED
VCR_DETECTED
VSYNCLOC
VLOCK
_NSTD
Bit Name
Bit Name
Bit 7
Bit 7
DDECSTAT2
DDECSTAT3
BLANKLVL_
SHIFT_DET
HLOCK
ECTED
Bit 6
Bit 6
Flag used to signal Vertical Synchronization Signal Capture
0: Vsync is not captured
Flag used to signal Horizontal PLL (detection) lock status
0: HPLL is out of lock
Flag used to signal Output PLL (line-locked) status
0: Output PLL is out of lock
Flag used to signal detection of either 50 Hz or 60 Hz signal
0: 60 Hz signal is detected.
Flag used to signal that standard is identified
0: Standard is not identified.
Identification (code) of Identified Standard
See the AUTOSTD[5:0] bits in the
The synchronisation block normally detects the input video parity by detecting the Vsync position with
respect to the Hsync. The Vsync position is normally at the beginning of line (0%) or middle of line (50%).
The built-in thresholds for Vsync position are 25% and 75%. When the Vysnc is actually close to these
limits, a bad parity detection may take place. This is the reason for this status bit.
When set, the Vsync is positioned between 20% - 30% OR 70%-80% of input video line.
When set, this bit indicates that the input video blank level is shifted during the VBI. This detection only
takes place when the shift is above a determined threshold and there is a low level of noise.
When set, this bit indicates that the input video is interlaced. When reset the input video is non interlaced.
This bit can potentially change value at each input video field
When set, this bit indicates that a DVD has been detected on the input.
When set, this bit indicates that a VCR has been detected on the input.
INTERLACE
D_DETECT
PLLLOCK
Bit 5
Bit 5
ED
Register Description
Register Description
DVD_DETE
5060ID
CTED
Bit 4
Bit 4
DDECCONT1
1: Vsync is captured
1: HPLL is in lock
1: Output PLL is in lock
1: 50 Hz signal is detected.
1: Standard is identified.
VCR_DETE
TVSTDID
CTED
Bit 3
Bit 3
Function
Function
register.
INSER_DET
ECTED
Bit 2
Bit 2
FB_DETEC
TVSTD[2:0]
Bit 1
Bit 1
TED
TRICKMOD_
DETECTED
STV2310
Bit 0
Bit 0