STV2310D STMicroelectronics, STV2310D Datasheet - Page 63

• Manufacturer Part Number: STV2310D
• Description: Video ICs Digital Video Decodr
• Manufacturer: STMicroelectronics
• Type: High Quality front end videor

Specifications of STV2310D

• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STV2310
CRCBOVER_EN
FBLANKMODE
[2:0]
YCRCB_MODE
PHSHFT_DIS
Address (hex): 06h
Reset Value (bin): 0000 0001
Bit Name
Bit 7
DDECCONT6
Bit 6
RGB enables the CRCB overload algorithm
This bit enables the RGB CrCb overload mechanism. This mechanism is used to prevent clipping on YCrCb
(when the input RGB signals are too large). The CrCb overload mechanism performs chroma measurement
during the video line to compute the correcting scale factor.
0: CRCB overload algorithm not active
1: CRCB overload algorithm active
Fast Blanking Mode Selection
The Fast Blanking mode is only operational when the STV2310 is not in Analog YCrCb mode. It also
depends on the programmed mode and the FB input value. See register
00x: Normal mixing mode between CVBS and RGB (Default)
(FB active during active line; soft mixing between 0 and 1)
01x: Saturated mode (mixing mode between CVBS and RGB)
(FB active and soft mixing from 0 to MIXSLOPE[7:0])
100: Static Mixer or Alpha Blending Mode 1
(FB inactive) Y
101: Static Mixer or Alpha Blending Mode 2
(FB inactive) Y
(Same relationship for Cr and Cb)
110: Forced CVBS (FB inactive) Y
111: Forced RGB (FB inactive) Y
YCrCb Mode Selection
When the STV2310 is in Analog YCrCb mode, Fast Blanking Mode is disabled.
0: YCrCb signals all either from CVBS or RGB. (Default)
1: YCrCb mode: Y from CVBS signal, Cr and Cb from RGB signal with priority over FB mode.
Phase Shift Option Disabled in Output PLL
This bit disables the phase jumps mechanism in the output PLL. Phase jumps are allowed when a phase
shift in the video input is transmitted in the data flow to the output PLL.
0: Phase shifts are enabled. (Default)
1: Phase shifts are disabled.
OUT
OUT
Bit 5
= alpha x Y
= alpha x Y
Register Description
RGB
CVBS
Bit 4
OUT
OUT
MIX_SLOPE[7:0]
+ (1-alpha) x Y
+ (1- alpha) x Y
= Y
= Y
RGB
CVBS
(idem for Cb,Cr)
(idem for Cb, Cr)
Bit 3
Function
CVBS
RGB
with alpha = MIXSLOPE[7:0]
Bit 2
DDECCONT6
Bit 1
.
Register List
Bit 0
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