FDD120AN15A0 Fairchild Semiconductor, FDD120AN15A0 Datasheet - Page 8

• Manufacturer Part Number: FDD120AN15A0
• Description: MOSFET N-CH 150V 14A D-PAK
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDD120AN15A0

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 120 mOhm @ 4A, 10V
• Drain To Source Voltage (vdss): 150V
• Current - Continuous Drain (id) @ 25° C: 14A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 14.5nC @ 10V
• Input Capacitance (ciss) @ Vds: 770pF @ 25V
• Power - Max: 65W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 0.12 Ohms
• Drain-source Breakdown Voltage: 150 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 14 A
• Power Dissipation: 65 W
• Maximum Operating Temperature: + 175 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2002 Fairchild Semiconductor Corporation
PSPICE Electrical Model
.SUBCKT FDD120AN15A0 2 1 3 ;
Ca 12 8 2.5e-10
Cb 15 14 2.5e-10
Cin 6 8 7.5e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 162
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 3e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2e-9
RLgate 1 9 30
RLdrain 2 5 10
RLsource 3 7 20
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 6.55e-2
Rgate 9 20 3.6
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 2.8e-2
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*25),3))}
.MODEL DbodyMOD D (IS=4E-12 N=1.07 RS=6.5e-3 TRS1=3.0e-3 TRS2=1.5e-6
+ CJO=5.5e-10 M=0.65 TT=5e-8 XTI=4.2)
.MODEL DbreakMOD D (RS=0.5 TRS1=1e-3 TRS2=-1e-6)
.MODEL DplcapMOD D (CJO=1.56e-10 IS=1.0e-30 N=10 M=0.62)
.MODEL MmedMOD NMOS (VTO=3.6 KP=1.8 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.6)
.MODEL MstroMOD NMOS (VTO=4.4 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.14 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=36 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1e-6)
.MODEL RdrainMOD RES (TC1=8.5e-3 TC2=2.5e-5)
.MODEL RSLCMOD RES (TC1=3.4e-3 TC2=1.5e-6)
.MODEL RsourceMOD RES (TC1=4.1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-3.6e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-4.1e-3 TC2=1.5e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.0 VOFF=-4.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-6.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.5 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
GATE
1
rev July 2002
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
6
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
51
5
5
+
-
MSTRO
14
51
21
RDRAIN
RSLC1
50
ESLC
16
8
MMED
8
EBREAK
IT
DBREAK
RSOURCE
MWEAK
17
RVTHRES
RBREAK
11
+
-
17
18
FDP120AN15A0 / FDD120AN15A0 Rev. B
7
+
18
-
22
RVTEMP
19
RLSOURCE
DBODY
LSOURCE
VBAT
RLDRAIN
LDRAIN
SOURCE
DRAIN
2
3