AD9912/PCBZ Analog Devices Inc, AD9912/PCBZ Datasheet - Page 7

• Manufacturer Part Number: AD9912/PCBZ
• Description: Eval Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9912/PCBZ

• Kit Features: Flexible System Clock I/P Accepts Crystal
• Supported Devices: AD9912
• Tool / Board Applications: Direct Digital Synthesizer
• Development Tool Type: Hardware - Eval/Demo Board
• Mcu Supported Families: AD9912
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9912
• Primary Attributes: 14-Bit DAC, 48-Bit Tuning Word Width
• Secondary Attributes: 1GHz, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Parameter
DAC OUTPUT CHARACTERISTICS
DIGITAL TIMING SPECIFICATIONS
SERIAL PORT TIMING SPECIFICATIONS
PROPAGATION DELAY
CMOS Output Driver
DCO Frequency Range (1
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Wideband SFDR
Narrow-Band SFDR
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Reset Assert to High-Z Time
SCLK Clock Rate (1/t
SCLK Pulse Width High, t
SCLK Pulse Width Low, t
SDO/SDIO to SCLK Setup Time, t
SDO/SDIO to SCLK Hold Time, t
SCLK Falling Edge to Valid Data on
CSB to SCLK Setup Time, t
CSB to SCLK Hold Time, t
CSB Minimum Pulse Width High, t
IO_UPDATE Pin Setup Time
IO_UPDATE Pin Hold Time
FDBK_IN to HSTL Output Driver
FDBK_IN to HSTL Output Driver with 2×
FDBK_IN to CMOS Output Driver
FDBK_IN Through S-Divider to CMOS
Frequency Tuning Word Update:
(from SCLK Rising Edge of the Final Bit)
IO_UPDATE Pin Rising Edge to DAC
Output
(AVDD3/Pin 37) @ 1.8 V
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
20.1 MHz Output
98.6 MHz Output
201.1 MHz Output
398.7 MHz Output
20.1 MHz Output
98.6 MHz Output
201.1 MHz Output
398.7 MHz Output
for S1 to S4 Configuration Pins
SDIO/SDO, t
Frequency Multiplier Enabled
Output Driver
DV
CLK
)
LOW
HIGH
H
st
S
Nyquist Zone)
DH
DS
PWH
−10
Min
0.008
45
0
AVSS −
0.50
8
8
1.93
1.9
1.34
−0.4
3
t
t
CLK
CLK
Typ
55
5
50
5
20
+0.5
−79
−67
−61
−59
−95
−96
−91
−86
15
18
60
25
2.8
7.3
8.0
8.6
60/f
S
Rev. F | Page 7 of 40
Max
65
6.8
450
31.7
+10
AVSS +
0.50
50
11
40
0.6
Unit
MHz
%
ns
MHz
Ω
pF
mA
% FS
μA
V
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
μs
μs
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
sec
sec
ns
ns
ns
ns
ns
Test Conditions/Comments
See Figure 28 for maximum toggle rate
With 20 pF load and up to 40 MHz
With 20 pF load
DAC lower limit is 0 Hz; however, the minimum slew rate
for FDBK_IN dictates the lower limit if using CMOS or HSTL
outputs
Single-ended (each pin internally terminated to AVSS)
Range depends on DAC R
Outputs connected to a transformer whose center tap is
grounded
See the Typical Performance Characteristics section
0 MHz to 500 MHz
0 MHz to 500 MHz
0 MHz to 500 MHz
0 MHz to 500 MHz
See the Typical Performance Characteristics section
±250 kHz
±250 kHz
±250 kHz
±250 kHz
Time from rising edge of RESET to high-Z on the S1, S2, S3,
S4 configuration pins
Refer to Figure 56 for all write-related serial port parameters;
maximum SCLK rate for readback is governed by t
Refer to Figure 54
t
t
S-divider bypassed
f
CLK
CLK
S
= system clock frequency in GHz
= period of SCLK in Hz
= period of SCLK in Hz
SET
resistor
AD9912
DV