LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 22

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
2.2.1
2.2.2
System Clocks/Reset/PME Controller
A clock module contained within the LAN9312 generates all the system clocks required by the device.
This module interfaces directly with the external 25MHz crystal/oscillator to generate the required clock
divisions for each internal module, with the exception of the 1588 clocks, which are generated in the
1588 Time Stamp Clock/Events module. A 16-bit general purpose timer and 32-bit free-running clock
are provided by this module for general purpose use.
The LAN9312 reset events are categorized as chip-level resets, multi-module resets, and single-
module resets.
A chip-level reset is initiated by assertion of any of the following input events:
A multi-module reset is initiated by assertion of the following:
A single-module reset is initiated by assertion of the following:
The LAN9312 supports numerous power management and wakeup features. The Port 1 & 2 PHYs
provide general power-down and energy detect power-down modes, which allow a reduction in PHY
power consumption. The Host MAC provides wake-up frame detection and magic packet detection
modes. The LAN9312 can be programmed to issue an external wake signal (PME) via several
methods, including wake on LAN, wake on link status change (energy detect), and magic packet
wakeup. The PME signal is ideal for triggering system power-up using remote Ethernet wakeup events.
System Interrupt Controller
The LAN9312 provides a multi-tier programmable interrupt structure which is controlled by the System
Interrupt Controller. At the top level are the
Register
modules. The LAN9312 is capable of generating interrupt events from the following:
Power-On Reset
nRST Pin Reset
Digital Reset - DIGITAL_RST (bit 0) in the
- Resets all LAN9312 sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual
PHY)
Soft Reset - SRST (bit 0) in the
- Resets the HBI, Host MAC, and System CSRs below address 100h
Port 2 PHY Reset - PHY2_RST (bit 2) in the
15) in the
- Resets the Port 2 PHY
Port 1 PHY Reset - PHY1_RST (bit 1) in the
15) in the
- Resets the Port 1 PHY
Virtual PHY Reset - VPHY_RST (bit 0) in the
the
Control Register (VPHY_BASIC_CTRL)
- Resets the Virtual PHY
1588 Time Stamp
Switch Fabric
Ethernet PHYs
GPIOs
Host MAC (FIFOs, power management)
General Purpose Timer
Power Management Control Register
(INT_EN). These registers aggregate and control all interrupts from the various LAN9312 sub-
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
Hardware Configuration Register (HW_CFG)
22
Interrupt Status Register (INT_STS)
(PMT_CTRL), or Reset (bit 15) in the
Reset Control Register (RESET_CTL)
Reset Control Register (RESET_CTL)
Reset Control Register (RESET_CTL)
Reset Control Register
(RESET_CTL), (bit 10) in
and
Virtual PHY Basic
Interrupt Enable
SMSC LAN9312
or Reset (bit
or Reset (bit
Datasheet