LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 119

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
9.6
EEPROM Address
01h
02h
03h
04h
05h
06h
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
Note: The switch fabric must be configured to pass magic packets to the Host MAC for this function
The Host MAC address is configured via the
Host MAC Address High Register
address of the Host MAC. The contents of these registers may be loaded directly by the host, or
optionally, by the EEPROM Loader from EEPROM at power-on (if a programmed EEPROM is
detected). The MAC address value loaded by the EEPROM Loader into the Host MAC address
registers (for host packet unicast qualification), is also loaded into the Switch Fabric MAC address
registers (for pause packet / flow control):
(SWITCH_MAC_ADDRL)
These two sets of registers are loaded simultaneously via the same EEPROM byte addresses.
Table 9.7
HMAC_ADDRH/SWITCH_MAC_ADDRH registers with respect to the reception of the Ethernet
physical address. Also shown is the correlation between the EEPROM addresses and
HMAC_ADDRL/SWITCH_MAC_ADDRL and HMAC_ADDRH/SWITCH_MAC_ADDRH registers.
For example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the HMAC_ADDRL and
HMAC_ADDRH registers would be programmed as shown in
automatically load this configuration from the EEPROM are also shown.
Host MAC Address
to operate properly.
below illustrates the byte ordering of the HMAC_ADDRL/SWITCH_MAC_ADDRL and
Table 9.7 EEPROM Byte Ordering and Register Correlation
SWITCH_MAC_ADDRL[23:16]
SWITCH_MAC_ADDRL[31:24]
SWITCH_MAC_ADDRH[15:8]
SWITCH_MAC_ADDRL[15:8]
Register Locations Written
SWITCH_MAC_ADDRH[7:0]
SWITCH_MAC_ADDRL[7:0]
and
HMAC_ADDRL[23:16]
HMAC_ADDRL[31:24]
HMAC_ADDRH[15:8]
HMAC_ADDRL[15:8]
HMAC_ADDRH[7:0]
HMAC_ADDRL[7:0]
Switch Fabric MAC Address High Register
DATASHEET
(HMAC_ADDRH). These registers contain the 48-bit physical
119
Host MAC Address Low Register (HMAC_ADDRL)
Switch Fabric MAC Address Low Register
Figure
Order of Reception on Ethernet
9.2. The values required to
(SWITCH_MAC_ADDRH).
Revision 1.7 (06-29-10)
2
3
1
4
5
6
nd
rd
th
th
th
st
and