LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 153

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
10.2.4.6
10.2.4.7
8-bits number_of_bursts
repeat (number_of_bursts)
Note: The starting address is a DWORD address. Appending two 0 bits will form the register address.
As an example, the following is a 3 burst sequence, with 1, 2, and 3 DWORDs starting at register
addresses 40h, 80h, and C0h respectively:
In order to avoid overwriting the Switch CSR register interface or the PHY Management Interface
(PMI), the EEPROM Loader waits until the CSR Busy bit of the
Register (SWITCH_CSR_CMD)
Register (PMI_ACCESS)
The EEPROM Loader checks that the EEPROM address space is not exceeded. If so, it will stop and
set the EEPROM Loader Address Overflow bit in the
address limit is based on the eeprom_size_strap which specifies a range of sizes. The address limit
is set to the largest value of the specified range.
EEPROM Loader Finished Wait-State
Once finished with the last burst, the EEPROM Loader will go into a wait-state and the EPC_BUSY
bit of the
Reset Sequence and EEPROM Loader
In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and
maintain consistency with the PHY and Virtual PHY registers, the following sequence is used:
1. After power-up or upon a hardware reset (nRST), the straps are sampled into the LAN9312 as
2. After the PLL is stable, the main chip reset is released and the EEPROM Loader reads the
3. The EEPROM Loader writes select Port 1/2 and Virtual PHY registers, as specified in
Note: Step 3 is also performed in the case of a RELOAD command or digital reset.
A5h, (Burst Sequence Valid Flag)
3h, (number_of_bursts)
16{10h, 1h}, (starting_address1 divided by 4 / count1)
11h, 12h, 13h, 14h, (4 x count1 of data)
16{20h, 2h}, (starting_address2 divided by 4 / count2)
21h, 22h, 23h, 24h, 25h, 26h, 27h, 28h, (4 x count2 of data)
16{30h, 3h}, (starting_address3 divided by 4 / count3)
31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3Ah, 3Bh, 3Ch (4 x count3 of data)
specified in
EEPROM and configures (overrides) the strap inputs.
Section 10.2.4.4.1
16-bits {starting_address[9:2] / count[7:0]}
repeat (count)
EEPROM Command Register (E2P_CMD)
8-bits data[31:24], 8-bits data[23:16], 8-bits data[15:8], 8-bits data[7:0]
Section 15.5.2, "Reset and Configuration Strap Timing," on page
and
are cleared before performing any register write.
Section
and the MII Busy bit of the
10.2.4.4.2, respectively.
DATASHEET
153
will be cleared.
EEPROM Command Register
Switch Fabric CSR Interface Command
PHY Management Interface Access
Revision 1.7 (06-29-10)
443.
(E2P_CMD). The