LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 192

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
14.2.3
14.2.3.1
31:30
29:28
27:16
15:14
BITS
13
RESERVED
GPIO 1588 Timer Interrupt Clear Enable 9-8
(GPIO_1588_TIMER_INT_CLEAR_EN[9:8])
These bits enable inputs on GPIO9 and GPIO8 to clear the
1588_TIMER_INT bit of the
(1588_INT_STS_EN). The polarity of these inputs is determined by
GPIO_INT_POL[9:8].
Note:
GPIO Interrupt Polarity 11-0 (GPIO_INT_POL[11:0])
These bits set the interrupt polarity of the 12 GPIO pins. The configured
level (high/low) will set the corresponding GPIO_INT bit in the
Purpose I/O Interrupt Status and Enable Register
0: Sets low logic level trigger on corresponding GPIO pin
1: Sets high logic level trigger on corresponding GPIO pin
GPIO_INT_POL[9:8] also determines the polarity of the GPIO IEEE 1588
time clock capture events and the GPIO 1588 Timer Interrupt Clear inputs.
Refer to
information.
1588 GPIO Output Enable 9-8 (1588_GPIO_OE[9:8])
These bits configure GPIO 9 and GPIO 8 to output 1588 clock compare
events.
0: Disables the output of 1588 clock compare events
1: Enables the output of 1588 clock compare events
Note:
GPIO 9 Clock Event Polarity (GPIO_EVENT_POL_9)
This bit determines if the 1588 clock event output on GPIO 9 is active high
or low.
0: 1588 clock event output active low
1: 1588 clock event output active high
GPIO/LED
This section details the General Purpose I/O (GPIO) and LED related System CSR’s.
General Purpose I/O Configuration Register (GPIO_CFG)
This read/write register configures the GPIO input and output pins. The polarity of the 12 GPIO pins
is configured here as well as the IEEE 1588 timestamping and clock compare event output properties
of the GPIO[9:8] pins.
Section 13.2, "GPIO Operation," on page 162
The GPIO must be configured as an input for this function to
operate. For the clear function, GPIO inputs are edge sensitive and
must be active for greater than 40 nS to be recognized.
These bits override the direction bits in the
Data & Direction Register (GPIO_DATA_DIR)
the GPIO buffer type (GPIOBUF[11:0]) in the
Configuration Register (GPIO_CFG)
Offset:
1588 Interrupt Status and Enable Register
1E0h
DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
DATASHEET
192
is not overridden.
Size:
(GPIO_INT_STS_EN).
General Purpose I/O
General Purpose I/O
register. However,
for additional
General
32 bits
TYPE
R/W
R/W
R/W
R/W
RO
SMSC LAN9312
DEFAULT
00b
Datasheet
0h
0h
1b
-