LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 180

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
14.2.2
14.2.2.1
31:30
29:28
27:16
BITS
15
RX End Alignment (RX_EA)
This field specifies the alignment that must be maintained on the last data
transfer of a buffer. The LAN9312 will add extra DWORD’s of data up to
the alignment specified in the table below. The host is responsible for
removing these extra DWORD’s. This mechanism can be used to maintain
cache line alignment on host processors.
Note:
RESERVED
RX DMA Count (RX_DMA_CNT)
This 12-bit field indicates the amount of data, in DWORD’s, to be
transferred out of the RX Data FIFO before asserting the
(RXD_INT). After being set, this field is decremented for each DWORD of
data that is read from the RX Data FIFO. This field can be overwritten with
a new value before it reaches zero.
Force RX Discard (RX_DUMP)
When a 1 is written to this bit, the RX Data and Status FIFO’s are cleared
of all pending data and the RX data and status pointers are cleared to zero.
Note:
Host MAC & FIFO’s
This section details the Host MAC and TX/RX FIFO related System CSR’s.
These Host Bus Interface accessible registers allow for the configuration of the TX/RX FIFO’s, Host
MAC and indirect access to the complete set of Host MAC CSR’s. The Host MAC CSR’s are
accessible through the Host Bus Interface via the
(MAC_CSR_CMD)
Note: For more information on the TX/RX FIFO’s, refer to
Note: The full list of Host MAC CSR’s are described in
Receive Configuration Register (RX_CFG)
This register controls the Host MAC receive engine.
VALUES
[31:30]
BIT
00
01
10
11
The desired RX End Alignment must be set before reading a
packet. The RX End Alignment can be changed between reading
receive packets, but must not be changed if the packet is partially
read.
Please refer to
Dump)," on page 134
of RX_DUMP.
Registers," on page
MAC," on page
Offset:
4-Byte Alignment
16-Byte Alignment
32-Byte Alignment
RESERVED
and
Section 9.9.1.2, "Force Receiver Discard (Receiver
112.
Host MAC CSR Interface Data Register
06Ch
DESCRIPTION
269. For more information on the Host MAC, refer to
for a detailed description regarding the use
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
END ALIGNMENT
DATASHEET
180
Size:
Host MAC CSR Interface Command Register
RX DMA Interrupt
Section 14.3, "Host MAC Control and Status
Section 14.1, "TX/RX FIFO
32 bits
(MAC_CSR_DATA).
TYPE
R/W
R/W
WO
RO
SC
Chapter 9, "Host
SMSC LAN9312
Ports".
DEFAULT
000h
00b
Datasheet
0b
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