DS21448N Maxim Integrated Products, DS21448N Datasheet - Page 9

• Manufacturer Part Number: DS21448N
• Description: Network Controller & Processor ICs 3.3V Quad E1-T1-J1 L ine Interface T1-E1-
• Manufacturer: Maxim Integrated Products

Specifications of DS21448N

• Product: Framer
• Number Of Transceivers: 4
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-C. Parallel Interface Mode Pin Description
RRING1–RRING4
BPCLK1–BPCLK4
TRING1–TRING4
D7/AD7–D0/AD0
RNEG1–RNEG4
RPOS1–RPOS4
PBEO1–PBEO4
RCL1/LOTC1–
RTIP1–RTIP4
RCL4/LOTC4
TTIP1–TTIP4
TXDIS/TEST
BIS0/BIS1
WR (R/W)
CS1–CS4
ALE (AS)
RD (DS)
A4–A0
MCLK
PBTS
HRST
PIN
INT
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Read Input (Data Strobe). RD and DS are active-low signals. DS is active low when in
nonmultiplexed, Motorola mode. See the bus timing diagrams in Section 10.
Write Input (Read/Write). WR is an active-low signal. See the bus timing diagrams in Section 10.
Address Latch Enable (Address Strobe). When using multiplexed bus mode (BIS0 = 0), this pin
serves to demultiplex the bus on a positive-going edge. In nonmultiplexed bus mode (BIS0 = 1),
ALE should be wired low.
Address Bus. In nonmultiplexed bus operation (BIS0 = 1), these pins serve as the address bus.
In multiplexed bus operation (BIS0 = 0), these pins are not used and should be wired low.
Data Bus/Address/Data Bus. In nonmultiplexed bus operation (BIS0 = 1), these pins serve as the
data bus. In multiplexed bus operation (BIS0 = 0), these pins serve as an 8-bit multiplexed
address/data bus.
Interrupt (INT). The interrupt flags the host controller during conditions and change of conditions
defined in the status register. It is an active-low, open-drain output.
Tri-State Control, Multifunctional. Set this pin high, with all CS1–CS4 inputs inactive, to tri-state
TTIP1–TTIP4 and TRING1–TRING4. Set this pin high with any of the CS1–CS4 inputs active to
tri-state all outputs and I/O pins (including the parallel control port). Set low for normal operation.
Hardware Reset. Bringing HRST low resets the DS21448, setting all control bits to the all-zeros
default state.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and for jitter attenuation. Use of a T1
1.544MHz clock source is optional (Note 1).
Bus Interface Select Bit 0 and 1. Used to select bus interface option. See
Parallel Bus Type Select. When using the parallel port, set PBTS high to select Motorola bus
timing; set low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS),
and WR (R/W) pins.
Chip Select 1. Must be low to read or write to channel 1 of the device. CS1 is an active-low
signal.
Chip Select 2. Must be low to read or write to channel 2 of the device. CS2 is an active-low
signal.
Chip Select 3. Must be low to read or write to channel 3 of the device. CS3 is an active-low
signal.
Chip Select 4. Must be low to read or write to channel 4 of the device. CS4 is an active-low
signal.
PRBS Bit-Error Output. The receiver constantly searches for a 2
PRBS, depending on the ETS bit setting (CCR1.7). It remains high if it is out of synchronization
with the PRBS pattern. It goes low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization cause a positive-going pulse (with same period as E1 or
T1 clock) synchronous with RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to logic 1.
Receive Carrier Loss/Loss-of-Transmit Clock. An output that toggles high during a receive carrier
loss (CCR2.7 = 0) or toggles high if the TCLK pin has not been toggled for 5µs ± 2µs (CCR2.7 =
1). CCR2.7 defaults to logic 0 when in hardware mode.
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a
1:1 transformer to the line. See Section
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output that is
referenced to RCLK selectable through CCR5.7 and CCR5.6.
Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up
transformer to the line. See Section
Receive Positive Data. These bits are updated on the rising edge (CCR2.0 = 0) or the falling
edge (CCR2.0 = 1) of RCLK with bipolar data out of the line interface. Set NRZE (CCR1.6) to 1
for NRZ applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or
EXZ) causes a positive-going pulse synchronous with RCLK at RNEG.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 =
1) of RCLK with the bipolar data out of the line interface. Set NRZE (CCR1.6) to 1 for NRZ
applications. In NRZ mode, data is output on RPOS, and a received error (BPV, CV, or EXZ)
causes a positive-going pulse synchronous with RCLK at RNEG.
9 of 60
7
for details.
7
for details.
FUNCTION
15
- 1 (E1) or a QRSS (T1)
Table 2-A
for details.