DS21448N Maxim Integrated Products, DS21448N Datasheet - Page 23

• Manufacturer Part Number: DS21448N
• Description: Network Controller & Processor ICs 3.3V Quad E1-T1-J1 L ine Interface T1-E1-
• Manufacturer: Maxim Integrated Products

Specifications of DS21448N

• Product: Framer
• Number Of Transceivers: 4
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CCR6 (05H): Common Control Register 6
5. STATUS REGISTERS
The three registers that contain information about the device’s real-time status are the status register (SR) and
receive information registers 1 and 2 (RIR1/RIR2). When a particular event has occurred (or is occurring), the
appropriate bit in one of these registers is set to 1. Some bits in SR, RIR1, and RIR2 are latched bits and some are
real-time bits (denoted in the following register descriptions). For latched status bits, when an event or an alarm
occurs, the bit is set to 1 and remains set until the user reads that bit. The bit is cleared when it is read, and it is not
set until the event has occurred again. Two of the latched status bits (RUA1 and RCL) remain set after reading if
the alarm is still present.
The user always precedes a read of any of the three status registers with a write. The byte written to the register
informs the DS21448 which bits the user wishes to read and have cleared. The user writes a byte to one of these
registers with a 1 in the bit positions to be read and a 0 in the other bit positions. When a 1 is written to a bit
location, that location is updated with the latest information. When a 0 is written to a bit position, that bit position is
not updated, and the previous value is held. A write to the status and information registers is immediately followed
by a read of the same register. The read result should be logically ANDed with the mask byte that was just written,
and this value should be written back into the same register to ensure that bit does indeed clear. This second write
step is necessary because the alarms and events in the status registers occur asynchronously with respect to their
access through the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor
to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS21448 with higher-order software languages.
ECRS2
ECRS1
ECRS0
ARLBE
(MSB)
NAME
RJAB
RLB
LLB
ALB
LLB
POSITION
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
CCR6.2
CCR6.1
CCR6.0
RLB
Local Loopback. In local loopback, transmit data is looped back to the receive path, passing
through the jitter attenuator if it is enabled. Data in the transmit path acts as normal. See
Section
0 = loopback disabled
1 = loopback enabled
Remote Loopback. In remote loopback, data output from the clock/data recovery circuitry is
looped back to the transmit path, passing through the jitter attenuator if it is enabled. Data in
the receive path acts as normal, while data presented at TPOS and TNEG is ignored. See
Section
0 = loopback disabled
1 = loopback enabled
Automatic Remote Loopback Enable and Reset. When this bit is set high, the device
automatically goes into remote loopback when it detects loop-up code programmed into the
receive loop-up code definition registers (RUPCD1 and RUPCD2) for a minimum of 5
seconds; it also sets the RIR2.1 status bit. Once it is in an RLB state, the bit remains in this
state until it has detected the loop code programmed into the receive loop-down code
definition registers (RDNCD1 and RDNCD2) for a minimum of 5 seconds, at which point it
forces the device out of RLB and clears RIR2.1. Toggling this bit from 1 to 0 resets the
automatic RLB circuitry. The action of the automatic remote loopback circuitry is logically
ORed with the RLB (CCR6.6) control bit (i.e., either one can cause a RLB to occur).
Analog Loopback. In analog loopback, signals at TTIP and TRING are internally connected to
RTIP and RRING. The incoming line signals at RTIP and RRING are ignored. The signals at
TTIP and TRING are transmitted as normal. See Section
0 = loopback disabled
1 = loopback enabled
RCLK Jitter Attenuator Bypass. This control bit allows the receive-recovered clock and data to
bypass the jitter attenuation, while still allowing the BPCLK output to use the jitter attenuator.
See Section
0 = disabled
1 = enabled
Error Count Register Select 2. See Section
Error Count Register Select 1. See Section
Error Count Register Select 0. See Section
ARLBE
6.2
6.2
for details.
for details.
7.3
for details.
ALB
23 of 60
RJAB
FUNCTION
6.4
6.4
6.4
for details.
for details.
for details.
ECRS2
6.2
for more details.
ECRS1
ECRS0
(LSB)