DS21448N Maxim Integrated Products, DS21448N Datasheet - Page 46

• Manufacturer Part Number: DS21448N
• Description: Network Controller & Processor ICs 3.3V Quad E1-T1-J1 L ine Interface T1-E1-
• Manufacturer: Maxim Integrated Products

Specifications of DS21448N

• Product: Framer
• Number Of Transceivers: 4
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXTEST. This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled through the update-IR state, the parallel outputs of
all digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The capture-
DR samples all digital inputs into the boundary scan register.
CLAMP. All digital outputs of the device are output data from the boundary scan parallel output while connecting
the bypass register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
HIGHZ. All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected
between JTDI and JTDO.
IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code is loaded into the identification register on the rising edge of
JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially
through JTDO. During test-logic-reset, the identification code is forced into the instruction register’s parallel output.
The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and
number of continuation bytes followed by 16 bits for the device and 4 bits for the version
the device ID code for the SCT devices.
Table 8-B. ID Code Structure
Table 8-C. Device ID Codes
8.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An
optional test register, the identification register, has been included with the DS21448 design. It is used with the
IDCODE instruction and the test-logic-reset state of the TAP controller.
Bypass Register
The bypass register is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that
provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the test-logic-reset state. See
and
Boundary Scan Register
The boundary scan register contains a shift register path and a latched parallel output for all control cells and digital
I/O cells, and is n bits in length. See
MSB
DS21448
DEVICE
(Contact Factory)
Table 8-C
Version
4 bits
for more information about bit usage.
16-BIT ID
0018
Device ID
16 bits
Table 8-D
for all cell bit locations and definitions.
46 of 60
00010100001
JEDEC
1
1
Table
LSB
8-B.
Table 8-C
Table 8-B
lists