DS21448N Maxim Integrated Products, DS21448N Datasheet - Page 43

• Manufacturer Part Number: DS21448N
• Description: Network Controller & Processor ICs 3.3V Quad E1-T1-J1 L ine Interface T1-E1-
• Manufacturer: Maxim Integrated Products

Specifications of DS21448N

• Product: Framer
• Number Of Transceivers: 4
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 400 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS21448 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE
contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port
(TAP) and Boundary Scan Architecture:
The TAP has the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions in
Section
1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 8-1. JTAG Block Diagram
8.1 JTAG TAP Controller State Machine
This section covers the operation of the TAP controller state machine. See
states described below. The TAP controller is a finite state machine that responds to the logic level at JTMS on the
rising edge of JTCLK
Test-Logic-Reset. Upon power-up, the TAP controller is in test-logic-reset state. The instruction register contains
the IDCODE instruction. All system logic of the device operates normally.
Run-Test-Idle. The run-test-idle is used between scan operations or during specific tests. The instruction register
and test registers remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK
moves the controller to the select-IR-scan state.
Test Access Port
TAP Controller
Instruction Register
1
for details. Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE
10kΩ
V
DD
(Table
JTDI
10kΩ
8-B).
V
DD
JTMS
TEST ACCESS PORT
IDENTIFICATION
CONTROLLER
BOUNDRY SCAN
INSTRUCTION
REGISTER
REGISTER
REGISTER
REGISTER
BYPASS
JTCLK
10kΩ
43 of 60
V
DD
JTRST
SELECT
OUTPUT ENABLE
Bypass Register
Boundary Scan Register
Device Identification Register
MUX
Figure 8-2
for details on each of the
(Table
JTDO
8-A). The DS21448